Exception Classifications For The Processor Core - Motorola MPC8240 User Manual

Exception Model
Table 5-7. Exception Classifications for the Processor Core
Synchronous/Asynchronous
Asynchronous, nonmaskable
Asynchronous, maskable
Synchronous
Although exceptions have other characteristics as well, such as whether they are maskable
or nonmaskable, the distinctions shown in Table 5-7 define categories of exceptions that the
processor core handles uniquely. Note that Table 5-7 includes no synchronous imprecise
instructions.
The processor core's exceptions, and conditions that cause them, are listed in Table 5-8.
Exception Vector Offset
Type (hex)
Reserved 00000
System reset 00100
Machine 00200
check
DSI 00300
ISI 00400
External 00500
interrupt
5-28
Precise/Imprecise
Imprecise
Precise
Precise
Table 5-8. Exceptions and Conditions
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A system reset is caused by the assertion of HRST_CPU, SRESET or sreset
(asserted by the EPIC unit).
A machine check exception is caused by the assertion of the NMI input signal or
the occurrence of internal errors as described in Chapter 13, "Error Handling." This
exception occurs when a machine check condition is detected, the error is enabled,
HID0[EMCP] is set, PICR1[MCP_EN] is set, and MSR[ME] is set. When one of
these errors occurs, the MPC8240 takes the exception and asserts the MCP output
signal.
The cause of a DSI exception can be determined by the bit settings in the DSISR,
listed as follows:
1 Set if the translation of an attempted access is not found in the primary hash
table entry group (HTEG), in the rehashed secondary HTEG, or in the range of
a DBAT register; otherwise cleared.
4 Set if a memory access is not permitted by the page or DBAT protection
mechanism; otherwise cleared.
5 Set by an eciwx or ecowx instruction if the access is to an address that is
marked as write-through or execution of a load/store instruction that accesses a
direct-store segment.
6 Set for a store operation and cleared for a load operation.
11 Set if eciwx or ecowx is used and EAR[E] is cleared.
An ISI exception is caused when an instruction fetch cannot be performed for any
of the following reasons:
• •The effective (logical) address cannot be translated. That is, there is a page
fault for this portion of the translation, so an ISI exception must be taken to load
the PTE (and possibly the page) into memory.
• •The fetch access is to a direct-store segment (indicated by SRR1[3] set).
• •The fetch access violates memory protection (indicated by SRR1[4] set). If the
key bits (Ks and Kp) in the segment register and the PP bits in the PTE are set
to prohibit read access, instructions cannot be fetched from this location.
An external interrupt is caused when MSR[EE] = 1 and the internal int signal is
asserted by the EPIC interrupt module to the processor core.
MPC8240 Integrated Processor User's Manual
Exception Type
Machine check
System reset
External interrupt
Decrementer
System management interrupt
Instruction-caused exceptions
Causing Conditions