Sdram Refresh Timing - Motorola MPC8240 User Manual

6.2.12.1 SDRAM Refresh Timing

The CBR refresh timing for SDRAM is controlled by the programmable timing parameter
MCCR3[REFREC]. REFREC represents the number of clock cycles from the refresh
command until a bank-activate command is allowed. The AC specifications of the specific
SDRAM device provides a minimum refresh-to-activate interval.
The MPC8240 implements bank staggering for CBR refreshes, as shown in Figure 6-18.
This reduces instantaneous current consumption for memory refresh operations.
SDRAM
CLK[0:3]
CKE
CS[0,7]
CS[1,6]
CS[2,5]
CS[3,4]
SDRAS
SDCAS
SDBA0
SDMA[12:0]
WE
DQM[0:7]
NOTE: Only one CS signal is asserted for the bank-activate and read commands.
Figure 6-18. SDRAM Bank Staggered CBR Refresh Timing
6.2.12.2 SDRAM Refresh and Power Saving Modes
The MPC8240's memory interface provides for sleep, doze, and nap power saving modes
defined for the local processor architecture. See Chapter 14, "Power Management," for
more information on these modes.
In doze and nap power saving modes, the MPC8240 supplies normal CBR refresh to
SDRAM. In sleep mode, the MPC8240 can be configured to use the SDRAM self-refresh
mode, provide normal refresh to SDRAM, or provide no refresh support. If the MPC8240
is configured to provide no refresh support in sleep mode, system software is responsible
for appropriately preserving SDRAM data, such as by copying to disk. Table 6-14
summarizes the MPC8240configuration bits relevant to power-saving modes.
REFREC
ROW ADDR
Chapter 6. MPC8240 Memory Interface
SDRAM Interface Operation
* See note
ACTORW
COL ADDR
6-33