Dar And Bcr Values—Double Pci Write - Motorola MPC8240 User Manual

DMA Register Descriptions
Figure 8-9 shows the bits in the BCRs.
0 0 0 0 0 0
31
Table 8-8 describes the bit settings for the BCRs.
Table 8-8. BCR Field Descriptions—Offsets 0x120, 0x220
Reset
Bits Name
Value
31–26 — All 0s
25–0 BCR All 0s
8.7.7 DAR and BCR Values—Double PCI Write
Note that when the DMA controller is programmed for local memory to PCI or PCI-to-PCI
memory transfers, certain values programmed in the DAR and BCR can cause the DMA
controller to write the last beat of data twice. Although no data corruption occurs and the
status register updates normally after the second beat of the double write has completed,
care must be taken if the device on the PCI bus is a FIFO-like structure.
The combination of DAR and BCR values that result in the double write can be determined
as follows:
(DAR + BCR) mod 0x20 = R,
where R= 0x09–0x0C, 0x11–0x14, or 0x19–0x1C
Example 1: DMA 42 (decimal) bytes from 0x0000_0000 to 0x8000_0000
R = (DAR + BCR) mod 0x20
R = (0x8000_0000 + 0x2A) mod 0x20
R = (2,147,483,648d + 42d) mod 32d
R = 10d = 0x0A
R = 0x0A which is in the range of 0x09–0x0C; therefore, double write of last beat to PCI
will occur.
Example 2: DMA 50 (decimal) bytes from 0x0009_0000 to 0x0009_4FE0.
R = (DAR + BCR) mod 0x20
R = (0x0009_4FE0 + 0x32) mod 0x20
R = (610,272d + 50d) mod 32d
R = 18d = 0x12
R = 0x12 which is in the range of 0x11–0x14; therefore, double write of last beat to PCI
will occur.
8-22
26 25
Figure 8-9. Byte Count Register (BCR)
R/W
RW Reserved
RW Byte count. Contains the number of bytes to transfer. The value in this register is
automatically decremented by the MPC8240 after each DMA read operation until
BCR = 0.
MPC8240 Integrated Processor User's Manual
BCR
Description
Reserved
0