E.2.5 Instruction Address Breakpoint Register (Iabr) - Motorola MPC8240 User Manual

Table E-18 describes the bit settings of the RPA register.
Bits
0–19
20–22
23
24
25–28
29
30–31

E.2.5 Instruction Address Breakpoint Register (IABR)

The IABR, shown in Figure E-26, controls the instruction address breakpoint exception.
IABR[CEA] holds an effective address to which each instruction is compared. The
exception is enabled by setting bit 30 of IABR. The exception is taken when there is an
instruction address breakpoint match on the next instruction to complete. The instruction
tagged with the match will not be completed before the breakpoint exception is taken.
0
Figure E-26. Instruction Address Breakpoint Register (IABR)
The bits in the IABR are defined as shown in Table E-19.
Table E-19. Instruction Address Breakpoint Register Bit Settings
Bit
0–29 Word address to be compared
30 IABR enabled. Setting this bit indicates that the IABR exception is enabled.
31 Reserved
E.3 MPC8240-Specific Registers
The hardware implementation-dependent registers (HIDx) are implemented differently in
the MPC8240 as described in the following subsections.
Table E-18. RPA Bit Settings
Name
RPN Physical page number from PTE
— Reserved
R Referenced bit from PTE
C Changed bit from PTE
WIMG Memory/cache access attribute bits
— Reserved
PP Page protection bits from PTE
CEA
Appendix E. Processor Core Register Summary
MPC8240-Specific Registers
Description
Description
Reserved
IE 0
29 30 31
E-23