Motorola MPC8240 User Manual page 10

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4.5 Embedded Utilities Memory Block Base Address Register-0x78 ................. 4-22
4.6 Memory Interface Configuration Registers ...................................................... 4-23
4.6.1 Memory Boundary Registers ........................................................................ 4-23
4.6.2 Memory Bank Enable Register-0xA0........................................................ 4-27
4.6.3 Memory Page Mode Register-0xA3 .......................................................... 4-28
4.7 Processor Interface Configuration Registers .................................................... 4-29
4.8 Error Handling Registers .................................................................................. 4-33
4.8.1 ECC Single-Bit Error Registers.................................................................... 4-33
4.8.2 Error Enabling and Detection Registers ....................................................... 4-34
4.9 Address Map B Options Register-0xE0 ......................................................... 4-41
4.10 Memory Control Configuration Registers ........................................................ 4-42
5.1 Overview............................................................................................................. 5-1
5.2 PowerPC Processor Core Features...................................................................... 5-3
5.2.1 Instruction Unit ............................................................................................... 5-5
5.2.2 Instruction Queue and Dispatch Unit.............................................................. 5-6
5.2.3 Branch Processing Unit (BPU) ....................................................................... 5-6
5.2.4 Independent Execution Units.......................................................................... 5-6
5.2.4.1 Integer Unit (IU) ......................................................................................... 5-7
5.2.4.2 Floating-Point Unit (FPU) .......................................................................... 5-7
5.2.4.3 Load/Store Unit (LSU) ............................................................................... 5-7
5.2.4.4 System Register Unit (SRU)....................................................................... 5-8
5.2.5 Completion Unit ............................................................................................. 5-8
5.2.6 Memory Subsystem Support........................................................................... 5-8
5.2.6.1 Memory Management Units (MMUs)........................................................ 5-8
5.2.6.2 Cache Units................................................................................................. 5-9
5.2.6.3 Peripheral Logic Bus Interface ................................................................... 5-9
5.2.6.3.1
5.2.6.3.2
5.2.6.3.3
5.3 Programming Model ......................................................................................... 5-10
5.3.1 Register Set ................................................................................................... 5-10
5.3.1.1 PowerPC Register Set............................................................................... 5-11
5.3.1.2 MPC8240-Specific Registers.................................................................... 5-13
5.3.1.2.1
5.3.1.2.2
5.3.1.2.3
5.3.1.2.4
5.3.2 PowerPC Instruction Set and Addressing Modes ......................................... 5-18
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CONTENTS
Chapter 5
PowerPC Processor Core
Peripheral Logic Bus Protocol................................................................ 5-9
Peripheral Logic Bus Data Transfers...................................................... 5-9
Peripheral Logic Bus Frequency .......................................................... 5-10
Hardware Implementation-Dependent Register 0 (HID0) ................... 5-13
Hardware Implementation-Dependent Register 1 (HID1) ................... 5-16
Hardware Implementation-Dependent Register 2 (HID2) ................... 5-17
Processor Version Register (PVR) ....................................................... 5-17
MPC8240 Integrated Processor User's Manual
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