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Figure 6-51 shows an example of a 2-Mbyte Flash system.
MDH[0:31]
MDL[0:31]
PAR[0:7]
A[20:0]
MPC8240
RCS0
RCS1
FOE
WE
Address
SDMA
Signals
12
(Outputs)
Logical
Names
20
19 18 17 16 15 14 13 12
Figure 6-51. 2-Mbyte Flash Memory System Including Parity Paths to
The MPC8240 supports an 8-, 32-, or 64-bit data path to bank 0. A configuration signal
(FOE) sampled at reset, determines the bus width of the ROM or Flash device (8-bit, 32-bit,
or 64-bit) in bank 0. The data bus width for ROM bank 1 is always 64 or 32 bits as
determined by the configuration signal, MDL[0], sampled at reset.
Data Path to/from SDRAM/DRAM Array
Parity Path to/from SDRAM/DRAM Array
Address Path to SDRAM/DRAM Array
Buffers
PAR
0
1
2
3
4
5
DRAM—8-Bit Mode
Chapter 6. MPC8240 Memory Interface
AR[20:0]
AR[20:0]
SDBA
6
7
0
10
9
8
AR[20:0]
11
10
9
8
ROM/Flash Interface Operation
A[20:0]
1M x 8
Flash
CE
WE
OE
Q[7:0]
MDH[0:7]
Q[7:0]
OE
WE
CE
1M x 8
Flash
A[20:0]
SDMA
7
6
5
4
3
2
7
6
5
4
3
2
1
0
1
0
6-75
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