Motorola MPC8240 User Manual page 496

Memory Interface Valid (MIV)
SDRAM_
CLK[0:3]
CS
FOE
A[19:0]
DATA
2 cycles
(constant)
DEBUG
ADDRESS
MIV
MAA
VALID
Figure 15-15. Example Flash Debug Address, MIV, and MAA Timings For
SDRAM_
CLK[0:3]
CS
FOE
V PP
5V
A[19:0]
DATA
WE
DEBUG
ADDRESS
MIV
MAA
NOTE:
1. V PP multiplexed by system logic with appropriate setup time to write cycle.
Figure 15-16. Example Flash Debug Address, MIV, and MAA Timings for Write
15-16
DATA0
ROMFAL
5 cycles
(constant)
VALID
Single-Byte Read
DATA0
ROMFAL
VALID
Operation
MPC8240 Integrated Processor User's Manual
2 cycles
(constant)
3 cycles
(constant)
VALID
DATA1
ROMFAL
VALID
VALID
13V
ROMNAL