Peripheral Logic Power Modes Summary - Motorola MPC8240 User Manual

Peripheral Logic Power Management
In doze, nap, and sleep modes, the peripheral logic always monitors the internal bus request
signal from the processor core. When it is asserted, for example due to the occurrence of
the decrementer exception, the peripheral logic exits its low power state and goes back to
the full-power state to service the request.
The MPC8240 does not support the broadcast of PCI special cycles related to low-power
operation. Thus, the PMCR1[NO_NAP_MSG] and PMCR1[NO_SLEEP_MSG] bits must
be set by initialization software (they are cleared upon reset) to indicate that the MPC8240
does not broadcast the HALT or sleep message commands on the PCI bus before entering
the nap or sleep modes, respectively.
Table 14-2 summarizes the functionality and transition criteria of the peripheral logic block
in all power states.
.
Table 14-2. Peripheral Logic Power Modes Summary
PM
Functioning Units
Mode
Full All units active
power
Doze PCI address decoding and bus arbiter
System RAM refreshing
Processor bus request and NMI monitoring
EPIC unit
2
I C unit
PLL
Nap PCI address decoding and bus arbiter
System RAM refreshing
Processor bus request and NMI monitoring
EPIC unit
2
I C unit
PLL
Sleep PCI bus arbiter
System RAM refreshing (can be disabled)
Processor bus request and NMI monitoring
EPIC unit
2
I C unit
PLL (can be disabled)
1
Programmable option based on value of PICR1[MCP_EN] = 1
2
A PCI access to memory in nap mode does not cause QACK to negate; consequently, it does not wake up the
processor core, and the processor core won't snoop this access. After servicing the PCI access, the peripheral
logic automatically returns to the nap mode.
14-8 MPC8240 Integrated Processor User's Manual
Activation Method
—
Controlled by software
(write to PMCR1)
Controlled by software
(write to PMCR1) and
processor core in nap or
sleep mode (QREQ
asserted)
Controlled by software
(write to PMCR1) and
processor core in nap or
sleep mode (QREQ
asserted)
Full-Power Wake Up
Method
—
PCI access to memory
Processor bus request
1
Assertion of NMI
Interrupt to EPIC
Hard Reset
2
PCI access to memory
Processor bus request
1
Assertion of NMI
Interrupt to EPIC
Hard Reset
Processor bus request
1
Assertion of NMI
Interrupt to EPIC
Hard Reset