Powerpc Processor Core - Motorola MPC8240 User Manual

Chapter 12
Central Control Unit
The MPC8240 uses internal buffering to store addresses and data moving through it and to
maximize opportunities for concurrent operations. A central control unit directs the flow of
transactions through the MPC8240 performing internal arbitration and coordinating the
internal and external snooping. This chapter describes the internal buffering and arbitration
logic of the MPC8240 central control unit (CCU). See Chapter 5, "PowerPC Processor
Core," for more detailed information on the kinds of internal transactions that are snooped
by the processor.
Note that the buffers described in this chapter don't include the internal data bus buffers in
the memory interface unit that are used for improved electrical performance (speed and
loading). For more information on these buffers, see Chapter 6, "MPC8240 Memory
Interface." Note also that in this chapter, the terminology local memory is used to denote
memory controlled by this MPC8240.
12.1 Internal Buffers
For most operations of the MPC8240, data is latched internally in one of eight data buffers.
Each of the eight internal data buffers has a corresponding address buffer. An additional
buffer stores the address of the most recent (or current) processor access to local memory.
All transactions entering the MPC8240 have their addresses stored in the internal address
buffers. The address buffers allow the addresses to be snooped as other transactions attempt
to go through the MPC8240. This is especially important for write transactions that enter
the MPC8240 because memory can be updated out-of-order with respect to other
transactions.
The CCU directs the bus snooping (provided snooping is enabled) for each PCI access to
local memory to enforce coherency between the PCI-initiated access and the L1 data cache.
All addresses are snooped in the order that they are received from the PCI bus. For systems
that do not require hardware-enforced coherency, snooping can be disabled by setting the
CF_NO_SNOOP parameter in PICR2. Note that if snooping is disabled, the PCI exclusive
access mechanism (the LOCK signal) does not affect the transaction. That is, the
transaction will complete, but the processor will not be prohibited from accessing the cache
line.
Chapter 12. Central Control Unit 12-1