Supported Fpm Or Edo Dram Organizations - Motorola MPC8240 User Manual

FPM or EDO DRAM Interface Operation
CAS[0:7]
RAS[7]
BANK7
RAS[6]
RAS[5]
RAS[4]
RAS[0:7]
RAS[3]
RAS[2]
RAS[1]
RAS[0]
BANK0
MDH[0:31], MDL[0:31]

6.3.1 Supported FPM or EDO DRAM Organizations

It is not necessary to use identical memory devices in each memory bank; individual
memory banks may be of differing sizes but not of different type (SDRAM). The MPC8240
can be configured to provide 9–13 row bits to a particular bank, and 7–12 column bits.
Table 6-17 summarizes the DRAM configurations supported by the MPC8240. This table
is not exhaustive, although it covers most available DRAMs. The largest DRAM that can
be supported is limited to 24 total address bits.
The MPC8240 can be configured at system start-up by using a memory-polling algorithm
or hard code in a boot ROM, to map correctly the size of each bank in memory. The
MPC8240 uses its bank map to assert the appropriate RAS[0:7] signals for memory
accesses according to the provided bank depths.
System software must also configure MCCR1 register in the MPC8240 at system start-up
to appropriately multiplex the row and column address bits for each bank for the devices
being used as shown in Table 6-17. Any unused banks should have their starting and ending
addresses programmed out of the range of memory banks in use. Otherwise memory may
become corrupted in the overlapping address range. Any unused banks should have their
starting and ending addresses programmed out of the range of memory banks in use.
Table 6-16 shows the unsupported multiplexed row and column address bit configurations
in the 32- and 64-bit data bus mode. They result in non-contiguous address spaces.
6-48
MDH(0:31)
32-bit Mode
64-bit Mode
Figure 6-31. DRAM Memory Organization
MPC8240 Integrated Processor User's Manual
256K –16M bits
MDL(0:31)
SDBA[1:0]
SDMA[12:0]
WE