Watchpoint Control Register Bit Field Definitions - Motorola MPC8240 User Manual

0 0 0 0 0 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Figure 16-11. Watchpoint Control Register (WP_CONTROL)—
Table 16-7 shows the bit field definitions for WP_CONTROL.
Table 16-7. Watchpoint Control Register Bit Field Definitions
Bits Name
31–29 —
28 DEBUG_ADDR_
27–25 —
24 WP_RUN
23–20 —
19–16 WP2_CNT[0–3]
15–12 —
0 0 0 0
Offsets 0xF_F048, 0xF48
Reset
R/W
Value
0b000 R Reserved
x RW Debug address disable. See Section 15.3, "Memory Debug
Address," for more information.
0 Debug address facility is enabled
1 Debug address facility is disabled
Note that the reset value of this bit is determined by the GNT4
signal. See Section 2.4, "Configuration Signals Sampled at
Reset," for more information.
0b000 R Reserved
0 R/W The watchpoint run bit is used to start and stop a watchpoint
scan. This is the only watchpoint register bit that should be
changed by software while the watchpoint facility is enabled
(WP_RUN = 1). This bit can also be toggled externally by pulsing
the TRIG_IN signal if the watchpoint facility is not in the HOLD
state.
When the watchpoint facility is in the HOLD state, pulsing
TRIG_IN causes the watchpoint facility to wake up and continue
or conclude its scan as programmed.
0 Start a watchpoint scan.
1 Stop a watchpoint scan.
0b0000 R Reserved
0b0000 R/W The watchpoint #2 counter field sets the initial value of the
countdown counter for watchpoint #2. This counter is only used in
watchpoint waterfall mode (WP_MODE = 0b01).
0000 16
0001 1
0010 2
...
1111 15
0b0000 R Reserved
Chapter 16. Programmable I/O and Watchpoint
0 0 0 0
9 8
Description
Watchpoint Registers
7 6 5 4 3 2 1 0
16-9