Watchpoint Registers - Motorola MPC8240 User Manual

16.2 Watchpoint Registers

The watchpoint facility is programmed through the watchpoint registers. These registers
allow the user to program watchpoint triggers and masks. Two sets of watchpoint triggers
and masks are supported, one for watchpoint #1 and another for watchpoint #2. In addition,
the watchpoint control register is used to configure the debug address function of the
MPC8240
The watchpoint registers are accessible from either the local bus or the PCI bus. The
WP_CONTROL[WP_RUN] bit is the only bit that can be changed while the watchpoint
facility is enabled (while WP_RUN = 1). Changing any other values in the watchpoint
registers while WP_RUN = 1 is not supported and results in unpredictable behavior.
16.2.1 Watchpoint Register Address Map
The watchpoint registers reside in an area of the embedded utilities block that is shared by
the memory data path diagnostic registers and are mapped as follows:
• Embedded utilities memory block (EUMBBAR contains base address) for local bus
accesses. Watchpoint registers located at offsets 0xF_F018 to 0xF_F048.
• Embedded utilities peripheral control and status registers (PCSRBAR contains base
address) for PCI bus accesses. Watchpoint registers located at offsets 0xF18 to
0xF48.
The offsets to individual watchpoint registers are listed in Table 16-2.
Local Bus PCI Bus
Offset Offset
0xF_F018 0xF18
0xF_F01C' 0xF1C
0xF_F020 0xF20
0xF_F024 0xF24
0xF_F030 0xF30
0xF_F034 0xF34
0xF_F038 0xF38
0xF_F03C 0xF3C
0xF_F048 0xF48
Table 16-2. Watchpoint Register Offsets
Program
Size
Access Size
(bytes)
(bytes)
4 4
4 4
4 4
4 4
4 4
4 4
4 4
4 4
4 1-, 2-, or 4-
Chapter 16. Programmable I/O and Watchpoint
Register
Register
Access
WP1_CNTL_TRIG
WP1_ADDR_TRIG
WP1_CTRL_MASK
WP1_ADDR_MASK
WP2_CNTL_TRIG
WP2_ADDR_TRIG
WP2_CTRL_MASK
WP2_ADDR_MASK
WP_CONTROL
Watchpoint Registers
Reset
Value
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x1000_0000
16-3