Motorola MPC8240 User Manual page 627

reserved bits, 4-1
summary of registers, list, 4-5, 4-8
EUMB registers
local processor control and status registers, 3-18
peripheral control and status registers, 3-19
runtime registers, 3-18
PCI configuration cycles
configuration space header, 7-21
configuration space header summary, 4-10
direct access method, 7-26
type 0 and 1 accesses, 7-23
PCI space addressing, 7-13
CR (condition register)
CR0/CR1 field definitions, E-4–E-5
CRn field, compare instructions, E-5
CSn (SDRAM command select) signals, 2-17
CTR (count register)
BO operand encodings, E-9
D
DA (debug address) signal, 2-30
DAR (destination address) register, 8-21
Data bus
bus transaction errors, 13-6
shared data bus, 12-2
termination by TEA, 13-10
Data path error injection/capture, 15-17
DCMP and ICMP registers, E-21
Debug
address, 15-5
address attribute signals, 15-2
address maps, 15-6
DH error capture monitor register, 15-19
DH error injection mask register, 15-17
DL error capture monitor register, 15-20
features list, 1-19
memory data path error injection/capture, 15-17
memory debug address, 1-20
parity error capture monitor register, 15-20
parity error injection mask register, 15-18
PCI address attribute signals, 15-3
Decrementer interrupt, 14-2
Device drivers, posted writes, 12-5
DEVSEL (device select) signal, 2-11, 7-13
DH error capture monitor register, 15-19
DH error injection mask register, 15-17
DHn/DLn (data bus) signals, 2-19
Disconnect, see Termination, 12-4
DL error capture monitor register, 15-20
DMA controller
block diagram, 8-2
burst wrap, 6-61
coherency, 8-8
DMA descriptors
INDEX
in big-endian mode, 8-14
in chaining mode, 8-12
in little-endian mode, 8-14
local memory to local memory transfers, 8-9
local memory to PCI, 8-9
modes
chaining mode, 8-5
direct mode, 8-4
operation, 8-3
overview, 8-1
PCI to local memory transfers, 8-9
PCI to PCI transfers, 8-9
transfer types, 8-9
DMISS and IMISS registers, E-21
DMR (DMA mode) register, 8-15
Doorbell registers
overview, 1-15
Doorbell registers, see also Registers
message register summary, 9-2
Doze mode, 1-18
DQMn (SDRAM data qualifier) signals, 2-17
DSR (DMA status) register, 8-18
E
EAR (external access register)
bit format, E-20
ECC single-bit error
registers, 4-33, 13-7
EDO DRAM interface
address multiplexing, 6-50
block diagram, 6-46
data interface, 6-54
DMA burst wrap, 6-61
ECC, 6-62
initialization, 6-55
organizations supported, 6-48
overview, 6-46
page mode retention, 6-61
parity, 6-61
power saving modes, 6-67
refresh timing, 6-66
RMW parity, 6-61
timing, 6-56
Effective address calculations, 5-18
EICR (interrupt configuration) register, 11-17
Embedded utilities memory block (EUMB)
local processor control and status registers, 3-18
peripheral control and status registers, 3-19
runtime registers, 3-18
Emulation mode
ESCR1/ESCR2 registers, 4-41
EPIC control signals, see Signals, 2-23
EPIC controller
block diagram, 11-3
Index Index-3