Pci-Accessible Configuration Registers; Processor Accessible Configuration Space - Motorola MPC8240 User Manual

Configuration Register Access
Reserved
Class Code
BIST Control
Output Driver Control
Memory Page Mode
Proc. Bus Error Status
PCI Bus Error Status
Figure 4-1. Processor Accessible Configuration Space
4.1.3.2 PCI-Accessible Configuration Registers
Table 4-3 lists the subset of configuration registers that are accessible from the PCI bus.
Note that configuration addresses not defined in Table 4-3 are reserved.
4-8
Device ID (0x0003)
PCI Status
Subclass Code
Header Type
Local Memory Base Address Register
Peripheral Control and Status Registers Base Address Register
Expansion ROM Base Address
MAX LAT MIN GNT
PCI Arbiter Control
PMCR2
Embedded Utilities Memory Block Base Address Register
Memory Starting Address
Memory Starting Address
Extended Memory Starting Address
Extended Memory Starting Address
Memory Ending Address
Memory Ending Address
Extended Memory Ending Address
Extended Memory Ending Address
Processor Interface Configuration Register 1
Processor Interface Configuration Register 2
Processor/PCI Error Address
Memory Control Configuration Register 1
Memory Control Configuration Register 2
Memory Control Configuration Register 3
Memory Control Configuration Register 4
MPC8240 Integrated Processor User's Manual
Vendor ID (0x1057)
PCI Command
Standard Programming Revision ID
Latency Timer Cache Line Size
Interrupt Pin Interrupt Line
Subordinate Bus # Bus Number
PMCR1
Clock Driver Control Register
Memory Bank Enable
ECC Single-Bit Trigger ECC Single-Bit Counter
Error Detection 1 Error Enabling 1
Error Detection 2 Error Enabling 2
Addr. Map B Options
Address
Offset (Hex)
00
04
08
0C
10
14
30
3C
40
44
70
74
78
80
84
88
8C
90
94
98
9C
A0
A4
A8
AC
B8
BC
C0
C4
C8
E0
F0
F4
F8
FC