Motorola MPC8240 User Manual page 12

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6.2.10 SDRAM In-Line ECC .................................................................................. 6-27
6.2.11 SDRAM Registered DIMM Mode ............................................................... 6-29
6.2.12 SDRAM Refresh........................................................................................... 6-31
6.2.12.1 SDRAM Refresh Timing .......................................................................... 6-33
6.2.12.2 SDRAM Refresh and Power Saving Modes............................................. 6-33
6.2.13 Processor-to-SDRAM Transaction Examples .............................................. 6-36
6.2.14 PCI-to-SDRAM Transaction Examples........................................................ 6-42
6.3 FPM or EDO DRAM Interface Operation........................................................ 6-46
6.3.1 Supported FPM or EDO DRAM Organizations ........................................... 6-48
6.3.2 FPM or EDO DRAM Address Multiplexing................................................ 6-50
6.3.2.1 Row Bit Multiplexing During The Row Phase (RAS) ............................. 6-50
6.3.2.2 Column Bit Multiplexing During the Column Phase (CAS).................... 6-51
6.3.2.3 Graphical View of the Row and Column Bit Multiplexing...................... 6-51
6.3.3 FPM or EDO Memory Data Interface .......................................................... 6-54
6.3.4 FPM or EDO DRAM Initialization .............................................................. 6-55
6.3.5 FPM or EDO DRAM Interface Timing........................................................ 6-56
6.3.6 DMA Burst Wrap.......................................................................................... 6-61
6.3.7 FPM or EDO DRAM Page Mode Retention ................................................ 6-61
6.3.8 FPM or EDO DRAM Parity and RMW Parity ............................................. 6-61
6.3.8.1 RMW Parity Latency Considerations ....................................................... 6-62
6.3.9 FPM or EDO ECC ........................................................................................ 6-62
6.3.9.1 FPM or EDO DRAM Interface Timing with ECC ................................... 6-64
6.3.10 FPM or EDO DRAM Refresh ...................................................................... 6-66
6.3.10.1 FPM or EDO Refresh Timing................................................................... 6-66
6.3.11 FPM or EDO DRAM Power Saving Modes................................................. 6-67
6.3.11.1 Configuration Parameters for DRAM Power Saving Modes ................... 6-67
6.3.11.2 DRAM Self-Refresh in Sleep Mode......................................................... 6-68
6.3.12 PCI-to-DRAM Transaction Examples.......................................................... 6-69
6.4 ROM/Flash Interface Operation ....................................................................... 6-73
6.4.1 ROM/Flash Address Multiplexing................................................................ 6-77
6.4.2 64 or 32-Bit ROM/Flash Interface Timing ................................................... 6-78
6.4.3 8-Bit ROM/Flash Interface Timing .............................................................. 6-81
6.4.4 ROM/Flash Interface Write Operations........................................................ 6-83
6.4.5 ROM/Flash Interface Write Timing ............................................................. 6-84
6.4.6 PCI-to-ROM/Port X Transaction Example................................................... 6-84
6.4.7 Port X Interface............................................................................................. 6-89
7.1 PCI Interface Overview ...................................................................................... 7-1
7.1.1 The MPC8240 as a PCI Initiator..................................................................... 7-2
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CONTENTS
Title
Chapter 7
PCI Bus Interface
MPC8240 Integrated Processor User's Manual
Page
Number