Global Timer Current Count Registers (Gtccrs) - Motorola MPC8240 User Manual

11.9.7.2 Global Timer Current Count Registers (GTCCRs)

The GTCRRs contain the current count for each of the four EPIC timers. Note that these
registers are read-only. The address offsets from EUMBBAR for the GTCCRs are
described in Table 11-12.
Figure 11-11 shows the bits of the GTCCRs.
T
31 30
Figure 11-11. Global Timer Current Count Register (GTCCR)
Table 11-13 describes the bit settings for the GTCCRs.
Reset
Bits Name
Value
31 T
30–0 COUNT All 0s
11.9.7.3 Global Timer Base Count Registers (GTBCRs)
The GTBCRs contain the base count for each of the four EPIC timers. This is the value
reloaded into the GTCCRs when they count down to zero. Note that these registers are
read/write. The address offsets from EUMBBAR for the GTBCRs are described in
Table 11-14.
Chapter 11. Embedded Programmable Interrupt Controller (EPIC) Unit
Table 11-12. EUMBBAR Offsets for GTCCRs
GTCCR
GTCCR0
GTCCR1
GTCCR2
GTCCR3
Table 11-13. GTCCR Field Descriptions
0 Toggle. This bit toggles whenever the current count decrements to zero.
Current timer count. This 31-bit field is decremented while the GTBCR[CI] bit is
zero. When the timer counts down to zero, this field is reloaded from the base
count register, the toggle bit is inverted, and an interrupt is generated (provided it
is not masked).
Table 11-14. EUMBBAR Offsets for GTBCRs
GTBCR
GTBCR0
GTBCR1
GTBCR2
GTBCR3
Offset
0x4 _1100
0x4_1140
0x4_1180
0x4_11C0
COUNT
Description
Offset
0x4_1110
0x4_1150
0x4_1190
0x4_11D0
Register Definitions
0
11-21