Overview - Motorola MPC8240 User Manual

Integrated host processor with integrated pci
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Chapter 13
Error Handling
The MPC8240 provides error detection and reporting on the three primary interfaces
(processor core, memory, and PCI). This chapter describes how the MPC8240 handles
different error conditions. Note that interrupts routed to the embedded programmable
interrupt controller (EPIC) are detected and reported by the EPIC and are not considered as
part of the internal error handling of the MPC8240 as described in this chapter. See
Chapter 11, "Embedded Programmable Interrupt Controller (EPIC) Unit," for more
information about the EPIC unit.

13.1 Overview

Errors detected by the MPC8240 are reported to the processor core by asserting an internal
machine check signal (mcp). The state of the internal machine check signal is externally
driven on the MCP output signal. The system error (SERR) and parity error (PERR) signals
are used to report errors on and to the PCI bus. The MPC8240 provides the NMI signal for
ISA bridges to report errors on the ISA bus. The MPC8240 internally synchronizes any
asynchronous error signals.
The PCI command, PCI status, and the error handling registers enable or disable the
reporting and detection of specific errors. These registers are described in Chapter 4,
"Configuration Registers."
The MPC8240 detects illegal transfer types from the processor, illegal Flash write
transactions, PCI address and data parity errors, accesses to memory addresses out of the
range of physical memory, memory parity errors, memory refresh overflow errors, ECC
errors, PCI master-abort cycles, and PCI received target-abort errors.
The MPC8240 latches the address and type of transaction that caused the error in the error
status registers to assist diagnostic and error handling software. Note that not all
transactions can be captured. See Section 4.8.2, "Error Enabling and Detection Registers,"
for more information. Section 2.2.5, "System Control and Power Management Signals,"
contains the signal definitions for the interrupt signals.
Chapter 13. Error Handling
13-1

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