Data Parity (Par[0:7])—Input - Motorola MPC8240 User Manual

2.2.2.10.2 Data Parity (PAR[0:7])—Input
Following are the state meaning and timing comments for PAR[0:7] as input signals.
State Meaning
Timing Comments Assertion/Negation—PAR[0:7] are valid concurrent with
2.2.2.11 ROM Address 19:12 (AR[19:12])—Output
The ROM address 19–12 (AR[19:12]) signals are output signals only for the ROM address
function. Note that these signals are both input and output signals for the memory parity
function (PAR[0:7]). Following are the state meaning and timing comments for AR[19:12]
as output signals.
State Meaning
Timing Comments Assertion/Negation—The ROM address is valid on assertion of
2.2.2.12 SDRAM Clock Enable (CKE)—Output
The SDRAM clock enable (CKE) signal is an output on the MPC8240 (and is also used as
a reset configuration input signal). CKE is part of the SDRAM command encoding. See
Section 6.2, "SDRAM Interface Operation," for more information. Following are the state
meaning and timing comments for the CKE output signal.
State Meaning
Timing Comments Assertion—CKE is valid on the rising edge of the
2.2.2.13 SDRAM Row Address Strobe (SDRAS)—Output
The SDRAM row address strobe (SDRAS) signal is an output on the MPC8240. Following
are the state meaning and timing comments for the SDRAS output signal.
State Meaning
Asserted/Negated—Represents the byte parity or ECC bits being
read from memory (PAR0 is the most-significant parity bit and
corresponds to byte lane 0 which is selected by CAS0 or DQM0).
MDH[0:31] and MDL[0:31].
Asserted/Negated—Represents bits 19–12 of the ROM/Flash
address. The other ROM address bits are provided by AR[10:0] as
shown in Section 6.4.1, "ROM/Flash Address Multiplexing."
RCS0 or RCS1.
Asserted—Enables the internal clock circuit of the SDRAM memory
device.
Negated—Disables the internal clock circuit of the SDRAM
memory device.
SDRAM_CLK[0:3] clock signals. See Section 6.2, "SDRAM
Interface Operation," for more information.
Asserted/Negated—SDRAS is part of the SDRAM command
encoding and is used for SDRAM bank selection during read or write
operations. See Section 6.2, "SDRAM Interface Operation," for
more information.
Chapter 2. Signal Descriptions and Clocking
Detailed Signal Descriptions
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