Memory Address Attribute Signal Timing - Motorola MPC8240 User Manual

Table 15-3. Memory Address Attribute Signal Encodings (Continued)
0
0
0
1
1
1
1

15.2.2 Memory Address Attribute Signal Timing

The memory address attribute signals have timing characteristics as shown in Figure 15-8
through Figure 15-16. These figures also show the relationship of MAA[0:2] with the MIV
signal. Note that the attribute signals are valid at the same time as the column address for
all DRAM accesses including single-beat, burst, 32- and 64-bit modes, page misses, page
hits and others. Note that for all ROM/Flash accesses the attribute signals are valid when
the address is valid.
15.2.3 PCI Address Attribute Signals
The PCI address attribute signals provide information about the source of the PCI operation
being performed by the MPC8240, and the encodings are defined in Table 15-4.
PMAA0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0 1 —
1 0 —
1 1 —
0 0 write
0 1 write
1 0 write
1 1 —
Table 15-4. PCI Attribute Signal Encodings
PMAA1 PMAA2
Operation
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
Chapter 15. Debug Features
Reserved
Reserved
Reserved
PCI memory write
DMA channel 0 memory write
DMA channel 1 memory write
Reserved
PCI
Definition
read Processor data load
read Processor touch load
read Processor instruction fetch
— reserved
— reserved
read DMA channel 0 PCI read
read DMA channel 1 PCI read
read PCI address bus invalid
write Processor data write
— reserved
— reserved
— reserved
— reserved
write DMA channel 0 PCI write
Address Attribute Signals
15-3