Inbound Free_Fifo Head Pointer Register (Ifhpr) - Motorola MPC8240 User Manual

Table 9-14 shows the bit settings for the IMIMR.
Table 9-14. IMIMR Field Descriptions—Offset 0x0_0104
Reset
Bits Name
Value
31–9 — All 0s
8 OFOM 0
7 IPOM 0
6 — 0
5 IPQIM 0
4 DMCM 0
3 IDIM 0
2 — 0
1 IM1IM 0
0 IM0IM 0

9.3.4.2.3 Inbound Free_FIFO Head Pointer Register (IFHPR)

Free MFAs are posted by the processor core to the inbound free_list FIFO pointed to by the
inbound free_FIFO head pointer register (IFHPR). The processor core is responsible for
updating the contents of IFHPR. Figure 9-11 shows the bits of the IFHPR.
I
31
Figure 9-11. Inbound Free_FIFO Head Pointer Register (IFHPR)
R/W
R Reserved
R/W Outbound free_list overflow mask
0 Outbound free_list overflow is allowed (and causes assertion of mcp).
1 Outbound free_list overflow is masked.
R/W Inbound post_list overflow mask
0 Inbound post_list overflow is allowed (and causes assertion of mcp).
1 Inbound post_list overflow is masked.
R Reserved
R/W Inbound post queue interrupt mask
0 Inbound post queue interrupt is allowed.
1 Inbound post queue interrupt is masked.
R/W Doorbell register machine check mask
0 Doorbell machine check (mcp) from IDBR[MC] is allowed.
1 Doorbell machine check (mcp) from IDBR[MC] is masked. When this
machine check condition is masked, the IMISR[DMC] is not set, regardless
of the state of IDBR[MC].
R/W Inbound doorbell interrupt mask
0 Inbound doorbell interrupt is allowed.
1 Inbound doorbell interrupt is masked.
R Reserved
R/W Inbound message 1 interrupt
0 Inbound message 1 interrupt is allowed.
1 Inbound message 1 interrupt is masked.
R/W Inbound message 0 interrupt
0 Inbound message 0 interrupt is allowed.
1 Inbound message 0 interrupt is masked.
QBA
20 19
Chapter 9. Message Unit (with I
Description
IFHP
O)
2
I O Interface
2
Reserved
0 0
2 1 0
9-15