Motorola MPC8240 User Manual page 636

IDBR (inbound doorbell), 9-2
ODBR (outbound door bell), 9-2
ECC single-bit error registers, 13-7
EPIC unit
EICR, 11-17
EPIC EVI, 11-18
external
IDRs, 11-25
IVPRs, 11-24
SDRs, 11-25
SVPRs, 11-24
FPR, 11-16
GCR, 11-16
GTBCR, 11-21
GTCCR, 11-21
GTDRs, 11-23
GTVPR, 11-22
IACK, 11-27
internal
IIDRs, 11-26
IIVPRs, 11-24
internal registers
IIDRs, 11-26
non-programmable registers
IPR, 11-9
IRR, 11-10
IS, 11-9
ISR, 11-10
PCTPR, 11-27
PI, 11-19
SVR, 11-19
TFRR, 11-20
ESCRs (emulation support configuration)
registers, 4-41
EUMB registers
local processor control and status registers, 3-18
peripheral control and status registers, 3-18, 3-19
runtime registers, 3-18
exception handling registers
DSISR, E-19
list, E-12
SRR0/SRR1, E-19
HASH1, 5-13, E-20
HASH2, 5-13, E-20
HID0, 5-13, E-24
HID1, 5-16, E-27
HID2, 5-17, E-28
2
I C interface
I2CADR, 10-7
I2CCR, 10-10
I2CDR, 10-13
I2CFDR, 10-8
I2CSR, 10-11
I O interface
2
Index-12
INDEX
MPC8240 Integrated Processor User's Manual
hardware registers, 9-5
IFHPR, 9-15
IFQPR, 9-11
IFTPR, 9-16
IMIMR, 9-14
IMISR, 9-12
IPHPR, 9-16
IPTPR, 9-17
MUCR, 9-20
OFHPR, 9-18
OFQPR, 9-12
OFTPR, 9-18
OMIMR, 9-10
OMISR, 9-9
OPHPR, 9-19
OPTPR, 9-19
QBAR, 9-21
register summary, 9-5
IABR, 5-13, E-20
ICMP, 5-13, E-20
IMISS, 5-13, E-20
implementation-specific registers, 5-13, E-20
DCMP/ICMP, E-21
DMISS/IMISS, E-21
HASH1/HASH2, E-22
IABR, E-23
RPA, E-22
JTAG
boundary-scan registers, 15-22
bypass register, 15-22
instruction register, 15-22
status register, 15-22
memory management registers
list, E-12
SRs, E-18
miscellaneous registers
DEC, E-19
EAR (optional), E-20
list, E-13
TBL/TBU, E-10
OEA register set, E-11
optional registers
EAR, E-20
PVR, 5-17, E-15
RPA, 5-13, E-20
supervisor-level
DCMP and ICMP, E-21
DEC, E-13, E-19
DMISS and IMISS, E-21
DSISR, E-19
EAR (optional), E-20
HASH1 and HASH2, E-22
IABR, E-23
MSR, E-13