Processor Nap Mode - Motorola MPC8240 User Manual

To return to full-power mode the following conditions must occur:
• Internal int or mcp signals asserted to the processor by the peripheral logic block,
NMI asserted, SMI asserted, or decrementer exception
• Hard reset or soft reset
• Transition to full-power state occurs within four processor cycles.

14.2.3.4 Processor Nap Mode

The nap mode disables the processor core except for the processor phase-locked loop (PLL)
and the time base/decrementer. The time base can be used to restore the processor core to
full-on state after a specified period.
Because bus snooping is disabled for nap and sleep mode, the peripheral logic block delays
the processor from entering into nap mode until all the peripheral logic internal buffers are
flushed and there is no outstanding transaction. Also, software must ensure that no PCI
master accesses main memory, unless software can guarantee that none of the accesses
would correspond to a modified line in the L1 cache.
When the peripheral logic block has ensured that snooping is no longer necessary, it allows
the processor to enter the nap (or sleep) mode and it causes the assertion of the MPC8240
QACK output signal for the duration of the nap mode period.
Nap mode is characterized by the following features:
• Time base/decrementer still enabled
• Most functional units disabled (including bus snooping)
• PLL running and locked to the internal sys_logic_clk signal
To enter the nap mode, the following conditions must occur:
• Set nap bit (HID0[9] = 1).
• Processor asserts internal request for nap or sleep mode to the peripheral logic.
• Peripheral logic must be programmed for nap or sleep mode.
• MPC8240 asserts quiesce acknowledge (QACK) output signal after flushing the
internal buffers in peripheral logic block.
• Processor core enters nap mode after several processor clocks. (Peripheral logic also
enters the nap or sleep mode.)
To return to full-power mode the following conditions must occur:
• Internal int or mcp signals asserted or QACK negated by the peripheral logic block,
SMI asserted, or decrementer exception
• Hard reset or soft reset
• Transition to full-power occurs within four processor cycles.
Chapter 14. Power Management
Processor Core Power Management
14-5