Motorola MPC8240 User Manual page 602

PowerPC Register Set
• Configuration registers
— Machine state register (MSR). The MSR defines the state of the processor. The
MSR can be modified by the Move to Machine State Register (mtmsr), System
Call (sc), and Return from Interrupt (rfi) instructions. It can be read by the Move
from Machine State Register (mfmsr) instruction.
Implementation Note—The 603e and MPC8240 define MSR[13] as the power
management enable (POW) bit and MSR[14] as the temporary GPR remapping
(TGPR) bit as shown in Table E-8.
— Processor version register (PVR). This register is a read-only register that
identifies the version (model) and revision level of the PowerPC processor.
Implementation Note—The MPC8240's processor version number is 0x0081;
the processor revision level starts at 0x0100 and is incremented for each revision
of the chip. The revision level is updated on all silicon revisions.
• Memory management registers
— Block-address translation (BAT) registers. The PowerPC OEA includes eight
block-address translation registers (BATs), consisting of four pairs of instruction
BATs (IBAT0U–IBAT3U and IBAT0L–IBAT3L) and four pairs of data BATs
(DBAT0U–DBAT3U and DBAT0L–DBAT3L). The SPR numbers for the BAT
registers are shown in Figure E-1.
— SDR1. The SDR1 register specifies the page table base address used in
virtual-to-physical address translation.
— Segment registers (SR). The PowerPC OEA defines sixteen 32-bit segment
registers (SR0–SR15). Note that the SRs are implemented on 32-bit
implementations only. The fields in the segment register are interpreted
differently depending on the value of bit 0.
• Exception handling registers
— Data address register (DAR). After a DSI or an alignment exception, DAR is set
to the effective address generated by the faulting instruction.
— SPRG0–SPRG3. The SPRG0–SPRG3 registers are provided for operating
system use.
— DSISR. The DSISR defines the cause of DSI and alignment exceptions.
— Machine status save/restore register 0 (SRR0). The SRR0 register is used to save
machine status on exceptions and to restore machine status when an rfi
instruction is executed.
— Machine status save/restore register 1 (SRR1). The SRR1 register is used to save
machine status on exceptions and to restore machine status when an rfi
instruction is executed.
Implementation Note—The 603e and MPC8240 implement the Key bit (bit 12)
in the SRR1 register in order to simplify the table search software.
E-12 MPC8240 Integrated Processor User's Manual