Processor Interface Configuration Registers - Motorola MPC8240 User Manual

4.7 Processor Interface Configuration Registers
The processor interface configuration registers (PICRs) control the programmable
parameters of the peripheral bus interface to the processor core. There are two 32-bit
PICRs—PICR1 and PICR2. Figure 4-17 shows the bits of PICR1.
Speculative PCI Reads
CF_APARK
0b1
LE_MODE
ST_GATH_EN
CF_DPARK
MCP_EN
FLASH_WR_EN
ADDRESS_MAP
PROC_TYPE
RCS0
0b00
11111111
31
Figure 4-17. Processor Interface Configuration Register 1 (PICR1)—0xA8
Table 4-26 describes the PICR1 bit settings.
Bits Name
31–24 —
addr<ab>
23–22 —
addr<aa>
21 —
20 RCS0
19 —
0 0
24 23 22 21 20 19 18 17 16 15
Table 4-26. Bit Settings for PICR1—0xA8
Reset
Value
All 1s Reserved
00 00 Must be cleared to 0b00
0 Reserved
x ROM location (read only.) This bit indicates the state of the ROM
location (RCS0) configuration signal during reset.
0 ROM is located on PCI bus.
1 ROM is located on processor/memory data bus.
0 Reserved
Chapter 4. Configuration Registers
Processor Interface Configuration Registers
0 0 0 0 0
13 12 11 10 9 8 7
Description
Reserved
1 0
6 5 4 3 2 1 0
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