Motorola MPC8240 User Manual page 29

Figure
Number
16-7 Watchpoint #1 Control Mask Register (WP1_CNTL_MASK)-
Offsets 0xF_F020, 0xF20 ........................................................................................... 16-6
16-8 Watchpoint #2 Control Mask Register (WP2_CNTL_MASK)-
Offsets 0xF_F038, 0xF38 ........................................................................................... 16-7
16-9 Watchpoint #1 Address Mask Register (WP1_ADDR_MASK)-
Offsets 0xF_F024, 0xF24 ........................................................................................... 16-8
16-10 Watchpoint #2 Address Mask Register (WP2_ADDR_MASK)-
Offsets 0xF_F03C, 0xF3C .......................................................................................... 16-8
16-11 Watchpoint Control Register (WP_CONTROL)-
Offsets 0xF_F048, 0xF48 ........................................................................................... 16-9
16-12 Watchpoint Facility State Diagram........................................................................... 16-12
16-13 Watchpoint Facility Block Diagram ......................................................................... 16-13
A-1 Processor Core Address Map ...................................................................................... A-3
A-2 PCI Memory Master Address Map ............................................................................. A-4
A-3 PCI I/O Master Address Map ..................................................................................... A-5
A-4 Direct-Access PCI Configuration Transaction ............................................................ A-6
B-1 Four-Byte Transfer to PCI Memory Space-Big-Endian Mode ..................................B-3
B-2 . Big-Endian Memory Image in Local Memory ...........................................................B-4
B-3 Big-Endian Memory Image in Big-Endian PCI Memory Space ..................................B-5
B-4 Munged Memory Image in Local Memory ..................................................................B-7
B-5 Little-Endian Memory Image in Little-Endian PCI Memory Space ............................B-8
B-6 One-Byte Transfer to PCI Memory Space-Little-Endian Mode ................................B-9
B-7 Two-Byte Transfer to PCI Memory Space-Little-Endian Mode .............................B-10
B-8 Four-Byte Transfer to PCI Memory Space-Little-Endian Mode .............................B-11
B-9 One-Byte Transfer to PCI I/O Space-Little-Endian Mode.......................................B-12
B-10 Two-Byte Transfer to PCI I/O Space-Little-Endian Mode......................................B-13
B-11 Four-Byte Transfer to PCI I/O Space-Little-Endian Mode......................................B-14
E-1 MPC8240 Processor Programming Model-Registers ................................................E-3
E-2 General-Purpose Registers (GPRs)...............................................................................E-4
E-3 Floating-Point Registers (FPRs) ...................................................................................E-4
E-4 Condition Register (CR) ...............................................................................................E-4
E-5 Floating-Point Status and Control Register (FPSCR)...................................................E-6
E-6 XER Register ................................................................................................................E-8
E-7 Link Register (LR)........................................................................................................E-9
E-8 Count Register (CTR) ...................................................................................................E-9
E-9 Time Base (TB)...........................................................................................................E-10
E-10 Machine State Register (MSR) ...................................................................................E-13
E-11 Processor Version Register (PVR)..............................................................................E-15
E-12 Upper BAT Register ...................................................................................................E-16
E-13 Lower BAT Register...................................................................................................E-16
E-14 SDR1 Register Format................................................................................................E-17
E-15 Segment Register Format (T = 0) ...............................................................................E-18
E-16 SPRG0-SPRG3 ..........................................................................................................E-18
ILLUSTRATIONS
Title
Illustrations
Page
Number
xxix