Fpm Dram Burst Read With Ecc - Motorola MPC8240 User Manual

Integrated host processor with integrated pci
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Figure 6-41 shows a FPM burst read operation.
MCLK
RAS
CAS
ADDR
DRAM DATA
INTERNAL
DATA BUS
Device driving data bus
TA
Figure 6-42 shows an EDO burst read operation.
MCLK
RAS
CAS
ADDR
DRAM DATA
INTERNAL
DATA BUS
TA
WE
Figure 6-42. EDO DRAM Burst Read Timing with ECC
ROW
COL
D0
DRAM
D0
Figure 6-41. FPM DRAM Burst Read with ECC
ROW
COL
DRAM
Device driving data bus
Chapter 6. MPC8240 Memory Interface
FPM or EDO DRAM Interface Operation
COL
COL
D1
D2
DRAM
DRAM
D0
D1
D1
D2
MPC8240
MPC8240
COL
COL
D0
D1
DRAM
D0
D0
D1
D1
MPC8240
MPC8240
COL
D3
DRAM
D2
D3
D3
MPC8240
MPC8240
COL
D2
D3
DRAM
DRAM
D2
D2
D3
D3
MPC8240
MPC8240
6-65

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