Sdram Interface Timing Intervals - Motorola MPC8240 User Manual

SDRAM Interface Operation
Timing Intervals
RDLAT The number of clock cycles from the read column command until the first data beat is
available on the internal processor core data bus.
RDLAT = SDRAM CAS latency + buffer mode delay + delay due to REGDIMM value. The
value of RDLAT should be additionally increased by one if MCCR3[REGDIMM] = 1.
Flow through
Registered
In-line ECC
REFREC The number of clock cycles from the refresh command until an activate command is
allowed. This can be calculated by referring to the AC specification of the SDRAM device.
The AC specification indicates a minimum refresh to activate interval in nanoseconds.
ACTORW The number of clock cycles from an activate command until a read or write command is
allowed. This interval will be listed (nS) in the AC specifications of the user's SDRAM.
ACTOPRE The number of clock cycles from an activate command until a precharge command is
allowed. This interval will be listed (nS) in the AC specifications of the user's SDRAM.
PRETOACT The number of clock cycles from a precharge command until an activate command is
allowed. This interval will be listed (nS) in the AC specifications of the user's SDRAM.
BSTOPRE The number of clock cycles to maintain a page open after an access. A subsequent
access can generate a page hit during this interval. A page hit reloads the BSTOPRE
counter. When the interval expires, a precharge is issued to the page.
The value of the above six parameters, (in whole clock cycles) must be set by boot code at
system start-up and kept in the MPC8240 configuration register space.
The following figures show SDRAM timing for various types of accesses. Figure 6-8 shows
a single-beat read operation.
6-22
Table 6-11. SDRAM Interface Timing Intervals
RDLAT Mode
MPC8240 Integrated Processor User's Manual
Definition
MCCR3[REGDIMM]
0
CL
CL + 1
CL + 2
1
–
CL + 2
CL + 3