Sdram Column Address Strobe (Sdcas)—Output - Motorola MPC8240 User Manual

Detailed Signal Descriptions
Timing Comments Assertion—SDRAS is valid on the rising edge of the SDRAM clock
2.2.2.14 SDRAM Column Address Strobe (SDCAS)—Output
The SDRAM column address strobe (SDCAS) signal is an output on the MPC8240.
Following are the state meaning and timing comments for the SDCAS output signal.
State Meaning
Timing Comments Assertion—For SDRAM, SDCAS is valid on the rising edge of the
2.2.2.15 ROM Bank 0 Select (RCS0)—Output
The ROM bank0 select (RCS0) signal is an output on the MPC8240 (and a reset
configuration input signal). Following are the state meaning and timing comments for the
RCS0 output signal.
State Meaning
Timing Comments Assertion—The MPC8240 asserts RCS0 at the start of a ROM/Flash
2.2.2.16 ROM Bank 1 Select (RCS1)—Output
The ROM bank 1 select (RCS1) signal is an output on the MPC8240. Following are the
state meaning and timing comments for the RCS1 output signal.
State Meaning
Timing Comments Assertion—The MPC8240 asserts RCS1 at the start of a ROM/Flash
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when a CSn signal is asserted.
Asserted—SDCAS is part of the SDRAM command encoding and is
used for SDRAM column selection during read or write operations.
See Section 6.2, "SDRAM Interface Operation," for more
information.
Negated—SDCAS is part of SDRAM command encoding used for
SDRAM column selection during read or write operations.
SDRAM clock when a CSn signal is asserted.
Asserted—Selects ROM bank 0 for a read access or Flash bank 0 for
a read or write access.
Negated—Deselects bank 0, indicating no pending memory access
to ROM/Flash.
access cycle.
Negation—Controlled by the ROMFAL and ROMNAL parameters
of the MCCR1 register.
Asserted—Selects ROM bank 1 for a read access or Flash bank 1 for
a read or write access.
Negated—Deselects bank 1, indicating no pending memory access
to ROM/Flash.
access cycle.
Negation—Controlled by the ROMFAL and ROMNAL parameters
of the MCCR1 register.
MPC8240 Integrated Processor User's Manual