A-4 Direct-Access Pci Configuration Transaction - Motorola MPC8240 User Manual

Configuration Accesses Using Direct Method
Processor physical address (A[0:31]) in the range
0x8080_0000–0x80FF_FFFF
1 000 0000
31 30 24 23 22
AD[31:0] signals
during address phase
0 000 0000
31 30 24 23 22
Figure A-4. Direct-Access PCI Configuration Transaction
During the address phase of a PCI configuration cycle, the MPC8240 decodes transactions
from the processor core in the address range from 0x8080_0000–0x80FF_FFFF, clears the
most-significant address bit, and copies the 30 low-order bits of the physical address
(without modification) onto the AD[31:0] signals. The two least-significant bits of the
internal peripheral logic bus address, A[30:31], must be 0b00. Note that the direct-access
method is limited to generating IDSEL on AD[11:22]. Also note that AD23 is always driven
high for direct-access configuration cycles. Therefore, no PCI device should use AD23 for
the IDSEL input on systems using address map A.
For type 1 translations, the MPC8240 copies the 30 high-order bits of the CONFIG_ADDR
register (without modification) onto the AD[31:2] signals during the address phase. The
MPC8240 automatically translates AD[1:0] into 0b01 during the address phase to indicate
a type 1 configuration cycle.
A-6
IDSEL–only one signal high
1
1 IDSEL–only one signal high
MPC8240 Integrated Processor User's Manual
Function number
Register number
11 10 8 7
Function/Register number
11 10
Reserved
00
2 1 0
00
2 1 0