Dynamic Power Management - Motorola MPC8240 User Manual

Processor Core Power Management

14.2.1 Dynamic Power Management

Dynamic power management (DPM) automatically powers up and down the individual
execution units of the MPC8240 processor core, based upon the contents of the instruction
stream. For example, if no floating-point instructions are being executed, the floating-point
unit is automatically powered down. Power is not actually removed from the execution unit;
instead, each execution unit has an independent clock input that is automatically controlled
on a clock-by-clock basis. Because CMOS circuits consume negligible power when they
are not switching, stopping the clock to an execution unit effectively eliminates its power
consumption. The operation of DPM is transparent to software or any external hardware.
Dynamic power management is enabled by setting bit 11 in HID0 following a hard reset
sequence.
14.2.2 Programmable Power Modes on Processor Core
The peripheral logic block can wake up the processor from a low power state through the
internal asynchronous interrupt (int) signal (generated by the EPIC unit), which transfers
program flow to the interrupt handler code. The appropriate mode then is set by the
software. The MPC8240 provides a second interrupt signal and interrupt vector for power
management—the system management interrupt (SMI). The MPC8240 also contains a
decrementer timer that allows it to enter the nap or doze mode for a specified period and
then return to full power operation through the decrementer interrupt exception.
The four processor power modes are selectable by setting the appropriate control bits in the
MSR and HID0 registers. The following is a brief description of the four power modes:
• Processor full-power—This is the default power state of the MPC8240. The
MPC8240 is fully powered and the internal functional units are operating at the full
processor clock speed. If the dynamic power management mode is enabled,
functional units that are idle automatically enter a low-power state without affecting
performance, software execution, or external hardware.
• Processor doze—All the functional units of the processor core are disabled except
for the time base/decrementer registers and the bus snooping logic. When the
processor is in doze mode, an asynchronous interrupt (signalled by the assertion of
int), a system management interrupt, a decrementer exception, a hard or soft reset,
or any machine check exception brings the MPC8240 into the full-power state. The
MPC8240 in doze mode maintains the PLL in a fully powered state and is locked to
the internal sys_logic_clk signal so a transition to the full-power state occurs within
four processor clock cycles.
• Processor nap—The nap mode further reduces power consumption by disabling bus
snooping by the processor, leaving only the time base register and the PLL in a
powered state. The MPC8240 returns to the full-power state upon receipt of an
interrupt (signalled by the assertion of int), a system management interrupt
(signalled by the assertion of SMI), a decrementer exception, a hard or soft reset, or
14-2 MPC8240 Integrated Processor User's Manual