Configuration Register Access In Little-Endian Mode - Motorola MPC8240 User Manual

Configuration Register Access
A subset of the configuration registers is accessible from the PCI bus through the use of PCI
configuration transactions. The MPC8240 responds to standard PCI configuration
transactions when its IDSEL signal is asserted. Table 4-3 provides a listing of configuration
registers accessible from the PCI bus.
Note that the address loaded into CONFIG_ADDR is used as a word address and does not
have byte granularity. Therefore, care must be taken when accessing configuration registers
that have a 1-or 2-byte size when the address of that register is not word-aligned. In this
case the stb or sth instructions must use an <ea> with the appropriate offset for that byte or
word, as shown in the following examples.
4.1.1 Configuration Register Access in Little-Endian Mode
When the processor and peripheral logic are in little-endian mode, the program should
access the configuration registers using the method described in Section 4.1,
"Configuration Register Access." This section provides several examples of configuration
register access in little-endian mode.
The configuration register address (CONFIG_ADDR) in the processor register should
appear (as data appears) in descending byte order (MSB to LSB) when it is stored to the
peripheral logic. The configuration data (CONFIG_DATA) appears in the processor
register in descending significance byte order (MSB to LSB) at the time it is loaded or
stored to the peripheral logic.
Example: Map B address map configuration sequence, 4-byte data write to register at
address offset 0xA8
Initial values: r0 contains 0x8000_00A8
r1 contains 0xFEC0_0000
r2 contains 0xFEE0_0000
r3 contains 0xAABB_CCDD
Register at 0xA8 contains 0xFFFF_FFFF (AB to A8)
Code sequence: stw
sync
stw
sync
Results:Address 0xFEC0_0000 contains 0x8000_00A8 (MSB to LSB)
Register at 0xA8 contains 0xAABB_CCDD (AB to A8)
Example: Map B address map configuration sequence, 1-byte data write to register at
address offset 0xAA
Initial values: r0 contains 0x8000_00A8
r1 contains 0xFEC0_0000
r2 contains 0xFEE0_0000
r3 contains 0xAABB_CCDD
Register at 0xA8 contains 0xFFFF_FFFF (AB to A8)
4-2
r0,0(r1)
r3,0(r2)
MPC8240 Integrated Processor User's Manual