Feature Reporting Register (Frr) - Motorola MPC8240 User Manual

Register Definitions
11.9 Register Definitions
The following sections describe the registers of the EPIC unit.

11.9.1 Feature Reporting Register (FRR)

The feature reporting register (FRR) provides information about the interrupt and processor
configurations. It also contains controller version information. Note that this register is
read-only. Figure 11-4 shows the bits in the FRR.
0 0 0 0 0
31 27 26
Figure 11-4. Feature Reporting Register (FRR)
Table 11-5 describes the bit settings for the FRR.
Table 11-5. FRR Field Descriptions—Offset 0x4_1000
Reset
Bits Name
Value
31–27 — All 0s
26–16 NIRQ 0x017
15–13 — All 0s
12–8 NCPU
7–0 VID
11.9.2 Global Configuration Register (GCR)
The GCR provides programming control for resetting the EPIC unit and for setting the
external interrupts mode. Note that this register is read/write. Figure 11-5 shows the bits in
the GCR.
R 0 M
31 30 29 28
Figure 11-5. Global Configuration Register (GCR)
11-16
NIRQ
Reserved
Number of interrupts. This field contains the maximum number of interrupt
sources supported. In the MPC8240, there are a maximum of 24 interrupts in use
at one time: the 4 internal sources (I
16 external sources. A zero in this field corresponds to one interrupt, and so on.
Thus the value of 0x017 corresponds to 24 interrupts.
Reserved
0x00 Number of CPUs. This field contains the number of the highest CPU supported.
Because one CPU is supported by the MPC8240's EPIC unit, the value is zero
corresponding to CPU 0.
0x02 Version ID for this interrupt controller. This value reports the level of OpenPIC
specification supported by this implementation. VID =2, representing version
level 1.2 of OpenPIC, for the initial release of the MPC8240.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MPC8240 Integrated Processor User's Manual
0 0 0 NCPU
16 15 13 12
Description
2
C, DMA (2), and MU), 4 timer sources and
Reserved
VID
8 7 0
Reserved
0