Processor Interface Errors - Motorola MPC8240 User Manual

Error Reporting
The processor/PCI error address register, the processor bus error status register, and the PCI
bus error status register together with ErrDR1[3] (processor/PCI cycle) and ErrDR2[7]
(invalid error address) provide additional information about a detected error condition.
When an error is detected, the associated information is latched inside these registers until
all error detection bits are cleared. Subsequent errors set the appropriate error detection bits,
but the bus error status and error address registers retain the information for the initial error
until all error detection bits are cleared.
As described in Section 13.2.2, "Processor Core Error Signal (mcp)," the MPC8240 asserts
mcp to the processor core when an enabled error condition has occurred during system
operation. The assertion of mcp depends upon whether the error handling registers of the
MPC8240 are set to report the specific error. Once asserted, the MPC8240 continues to
assert mcp until the MPC8240 decodes a read from the processor to the machine check
exception vector (0xnnn0_0200). When it decodes a processor read from the machine
check exception vector, the MPC8240 negates mcp. Note that if the system ROM space is
located on the PCI bus, then a processor read from 0xFFF0_0200 will not negate the mcp
signal. In this case, the machine check exception handler must perform a dummy read from
0x0000_0200 to cause the negation of mcp.
Until all the error detection bits are cleared, the MPC8240 does not report subsequent errors
by reasserting mcp.
Certain events in the inbound portion of the message unit can cause the assertion of mcp.
These events can mask (or be masked by) other errors until the machine check exception
handler clears them.
In addition to the error detection bits, the MPC8240 reports the assertion of NMI to the
processor core by asserting mcp (if enabled). Note that NMI assertion is not recorded in the
MPC8240's error detection bits. Reporting NMI assertion (by mcp) can be masked by any
error detection bits that are set.

13.3.1 Processor Interface Errors

The processor interface of the MPC8240 detects unsupported processor bus transaction
errors, Flash write errors, and write parity errors. In these cases, both ErrDR1[3] and
ErrDR2[7] are cleared, indicating that the error is due to a processor transaction and the
address in the processor/PCI error address register is valid.Internally, the MPC8240 asserts
transfer acknowledge (provided PICR1[10] = 0) to terminate the data tenure.
13.3.1.1 Processor Transaction Error
When a processor transaction error occurs, ErrDR1[1–0] is set to reflect the error type.
Unsupported processor bus transactions include writes to the PCI interrupt-acknowledge
space (0xBFFF_FFFn using address map A or 0xFEFn_nnnn using address map B) and
attempts to execute the graphic read or graphic write instructions (eciwx or ecowx).
13-6 MPC8240 Integrated Processor User's Manual