Pci Command Register-Offset 0X04 - Motorola MPC8240 User Manual

Table 4-4. PCI Configuration Space Header Summary (Continued)
Address
Register Name
Offset
0x30 Expansion ROM base
address
0x34–0x3B —
0x3C Interrupt line
0x3D Interrupt pin
0x3E MIN GNT
0x3F MAX LAT
0x43 —
System software may need to scan the PCI bus to determine what devices are actually
present. To do this, the configuration software must read the vendor id in each possible PCI
slot. If there is no response to a read of an empty slot, the MPC8240 returns 0xFFFF (the
invalid vendor id). Any configuration write cycle to a reserved register is completed
normally and the data is discarded.
Note that the MPC8240 must not issue PCI configuration transactions to itself (that is, for
PCI configuration transactions initiated by the MPC8240, its IDSEL input signal must not
be asserted).
4.2.1 PCI Command Register—Offset 0x04
The following subsections describe the MPC8240 PCI configuration registers in detail.
The 2-byte PCI command register, shown in Figure 4-3, provides control over the ability to
generate and respond to PCI cycles. Table 4-5 describes the bits of the PCI command
register.
Memory-write-and-invalidate
Parity error response
15
This register is read-only. The default value has 0b0 in bit 0, defining the
expansion ROM base address register as disabled in the MPC8240.
Reserved for future use by PCI
Contains interrupt line routing information
Indicates which interrupt pin the device (or function) uses
(0x00 = no interrupt pin)
Specifies the length of the device's burst period
(0x00 indicates that the MPC8240 has no major requirements for the
settings of latency timers.)
Specifies how often the device needs to gain access to the PCI bus
(0x00 indicates that the MPC8240 has no major requirements for the
settings of latency timers)
Reserved on the MPC8240
SERR
Fast back-to-back
0 0 0 0_0 0
10 9 8
Figure 4-3. PCI Command Register—0x04
Chapter 4. Configuration Registers
PCI Interface Configuration Registers
Description
0 0
7 6 5 4 3 2 1
Reserved
Special cycles
Bus master
Memory space
I/O space
0
4-11