E.1.3.2 Processor Version Register (Pvr) - Motorola MPC8240 User Manual

Reset
Bit(s) Name
Value
28–2 — 0
9
30 RI 0
31 LE 0
The floating-point exception mode bits (FE0–FE1) are interpreted as shown in Table E-9.
Table E-9. Floating-Point Exception Mode Bits

E.1.3.2 Processor Version Register (PVR)

The processor version register (PVR) is a 32-bit, read-only register that contains a value
identifying the specific version (model) and revision level of the PowerPC processor as
shown in Figure E-11.
0
Figure E-11. Processor Version Register (PVR)
Software can identify the MPC8240's processor core by reading the processor version
register (PVR). The MPC8240's processor version number is 0x0081; the processor
revision level starts at 0x0100 and is incremented for each revision of the chip. This
information is useful for data cache flushing routines for identifying the size of the cache
and identifying this processor as one that supports cache locking.
E.1.3.3 BAT Registers
Figure E-12 and Figure E-13 show the format of the upper and lower BAT registers for
32-bit PowerPC processors.
Table E-8. MSR Bit Settings (Continued)
Reserved
Recoverable exception (for system reset and machine check exceptions).
0 Exception is not recoverable.
1 Exception is recoverable.
Little-endian mode enable
0 The processor runs in big-endian mode.
1 The processor runs in little-endian mode.
FE0 FE1
0 0 Floating-point exceptions disabled
0 1 Floating-point imprecise nonrecoverable
1 0 Floating-point imprecise recoverable
1 1 Floating-point precise mode
Version
Appendix E. Processor Core Register Summary
Description
Mode
15 16
PowerPC Register Set
Revision
31
E-15