Motorola MPC8240 User Manual page 149

Table 4-17. Output Driver Control Register Bit Definitions—0x73 (Continued)
Bits Name
4 DRV_MEM_CTRL_2
3 DRV_PCI_CLK_1
2 DRV_PCI_CLK_2
1 DRV_MEM_CLK_1
0 DRV_MEM_CLK_2
Output/Clock Driver and Miscellaneous I/O Control Registers
Reset
Value
x Driver capability for address signals (RAS/CS[0:7], CAS/DQM[0:7], WE,
FOE, RCS0, SDBA0, AR[19:12], SDRAS, SDCAS, CKE, AS,
SDMA[12:0]).
The meaning of this bit setting depends on the setting of
DRV_MEM_CTRL_1. The two bits and the meaning of their combined
settings for the address signals are shown below:
DRV_MEM_CTRL_[1–2]:
11 8-Ω drive capability
10 13.3-Ω drive capability
01 20-Ω drive capability
00 40-Ω drive capability
The initial value of DRV_MEM_CTRL[1–2] is determined by the PMAA0
and PMAA1 reset configuration pins, respectively.
1 Driver capability is controlled in combination with DRV_PCI_CLK_2 as
shown.
1 Driver capability is controlled in combination with DRV_PCI_CLK_1, and
controls drive strength of PCI_CLK[0:4] and PCI_CLK_SYNC_OUT.
DRV_PCI_CLK_[1–2]:
11 8-Ω drive capability
10 13.3-Ω drive capability
01 20-Ω drive capability
00 40-Ω drive capability
1 Driver capability is controlled in combination with DRV_MEM_CLK_2 as
shown.
1 Driver capability is controlled in combination with DRV_MEM_CLK_1,
and controls drive strength of SDRAM_CLK[0:3] and
SDRAM_SYNC_OUT.
DRV_MEM_CLK_[1–2]:
11 8-Ω drive capability
10 13.3-Ω drive capability
01 20-Ω drive capability
00 40-Ω drive capability
Chapter 4. Configuration Registers
Description
4-21