Basic Transfer Control - Motorola MPC8240 User Manual

PCI Bus Protocol

7.3.1 Basic Transfer Control

The basic PCI bus transfer mechanism is a burst. A burst is composed of an address phase
followed by one or more data phases. Fundamentally, all PCI data transfers are controlled
by three signals—FRAME (frame), IRDY (initiator ready), and TRDY (target ready). An
initiator asserts FRAME to indicate the beginning of a PCI bus transaction and negates
FRAME to indicate the end of a PCI bus transaction. An initiator negates IRDY to force
wait cycles. A target negates TRDY to force wait cycles.
The PCI bus is considered idle when both FRAME and IRDY are negated. The first clock
cycle in which FRAME is asserted indicates the beginning of the address phase. The
address and bus command code are transferred in that first cycle. The next cycle begins the
first of one or more data phases. Data is transferred between initiator and target in each
cycle that both IRDY and TRDY are asserted. Wait cycles may be inserted in a data phase
by the initiator (by negating IRDY) or by the target (by negating TRDY).
Once an initiator has asserted IRDY, it cannot change IRDY or FRAME until the current
data phase completes regardless of the state of TRDY. Once a target has asserted TRDY or
STOP, it cannot change DEVSEL, TRDY, or STOP until the current data phase completes.
In simpler terms, once an initiator or target has committed to the data transfer, it cannot
change its mind.
When the initiator intends to complete only one more data transfer (which could be
immediately after the address phase), FRAME is negated and IRDY is asserted (or kept
asserted) indicating the initiator is ready. After the target indicates the final data transfer (by
asserting TRDY), the PCI bus may return to the idle state (both FRAME and IRDY are
negated) unless a fast back-to-back transaction is in progress. In the case of a fast
back-to-back transaction, an address phase immediately follows the last data phase.
7.3.2 PCI Bus Commands
A PCI bus command is encoded in the C/BE[3:0] signals during the address phase of a PCI
transaction. The bus command indicates to the target the type of transaction the initiator is
requesting. Table 7-2 describes the PCI bus commands as implemented by the MPC8240.
Chapter 7. PCI Bus Interface 7-9