Peripheral Blocks; Figure 1-2 Dsp56800 Core Block Diagram - Motorola DSP56800 Manual

Clock & Control
PAB
Program
XAB1
Memory
XAB2
PDB
Data Memory
CGDB
PGDB
Peripherals
XDB2
1.1.2

Peripheral Blocks

The following peripheral blocks are available for members of the DSP56800 16-bit Family:
• Program ROM and RAM modules
• Bootstrap ROM for program RAM parts
• Data ROM and RAM modules
• Phase-locked loop (PLL) module
— 32.0 kHz and 38.4 kHz crystals accepted
— Crystal frequencies
— Programmable multiplication factor
— Three pins required (SXFC, V
Program
Controller
SR OMR
Instr. Decoder
And
LA LC
Interrupt Unit
PC HWS
Data
ALU
Bus And Bit
Manipulation
Unit
Y1 Y0
OnCE
Figure 1-2. DSP56800 Core Block Diagram
≥
1 MHz accepted
, and GNDS)
DDS
Introduction
DSP56800 Family Architecture
AGU
M01 N
MOD.
+/-
ALU
Clock Gen.
Limiter
X0 A2 A1 A0 B2 B1 B0
SP
R0
R1
R2
R3
External
Bus
Interface
MAC
and
ALU
AA0006
1-3