Motorola MC68306 Manuals

Motorola MC68306 Manuals

Manuals and User Guides for Motorola MC68306. We have 1 Motorola MC68306 manual available for free PDF download: User Manual

Motorola MC68306 User Manual

Motorola MC68306 User Manual (191 pages)

Integrated EC000 Processor

Brand: Motorola | Category: Computer Hardware | Size: 1.24 MB

Table of Contents

Table of Contents
4
Introduction

16
- Figure 1-1. MC68306 Simplified Block Diagram
  16
- MC68EC000 Core Processor
  17
- On-Chip Peripherals
  18
- Serial Module
  18
- Chip Selects
  19
- DRAM Controller
  19
- Parallel Ports
  19
- Interrupt Controller
  19
- Clock
  19
- Bus Timeout Monitor
  20
- IEEE 1149.1 Test
  20
Signal Descriptions

21
- Figure 2-1. MC68306 Detailed Block Diagram
  22
- Table 2-1. Bus Signal Summary
  23
- Table 2-2. Chip Select Signal Summary
  23
- Table 2-3. DRAM Controller Signal Summary
  23
- Table 2-4. Interrupt and Parallel Port Signal Summary
  24
- Table 2-5. Clock and Mode Control Signal Summary
  24
- Bus Signals
  25
- Address Bus (A23-A1)
  25
- Table 2-6. Serial Module Signal Summary
  25
- Table 2-7. JTAG Signal Summary
  25
- Address Strobe (AS)
  26
- Bus Error (BERR )
  26
- Bus Request (BR)
  26
- Bus Grant (BG )
  26
- Bus Grant Acknowledge (BGACK)
  26
- Data Bus (D15-D0)
  27
- Data Transfer Acknowledge (DTACK)
  27
- DRAM Multiplexed Address Bus (DRAMA14-DRAMA0)
  27
- Processor Function Codes (FC2-FC0)
  27
- Halt (HALT)
  27
- Table 2-8. Function Code Outputs
  27
- Read/Write (R/W)
  28
- Table 2-9. Data Strobe Control of Data Bus
  28
- Lower Byte Write (LW )
  29
- Output Enable (OE)
  29
- Reset (RESET )
  29
- Chip Select Signals
  29
- DRAM Controller Signals
  29
- Column Address Strobe (CAS1- CAS0 )
  29
- Row Address Strobe (RAS1 -RAS0)
  29
- DRAM Write Signal (DRAMW)
  29
- Interrupt Control and Parallel Port Signals
  29
- Interrupt Request (IRQ7-IRQ1)
  30
- Interrupt Acknowledge (IACK7-IACK1)
  30
- Port a Signals (PA7-PA0)
  30
- Port B (PB7-PB0)
  30
- Clock and Mode Control Signals
  30
- Crystal Oscillator (EXTAL, XTAL)
  30
- Clock out (CLKOUT)
  30
- Address Mode (AMODE)
  30
- Serial Module Signals
  30
- Channel a Receiver Serial-Data Input (Rxda)
  31
- Channel a Transmitter Serial-Data Output (Txda)
  31
- Channel B Receiver Serial-Data Input (Rxdb)
  31
- Channel B Transmitter Serial-Data Output (Txdb)
  31
- Ctsa
  31
- Rtsa
  31
- Ctsb
  31
- Rtsb
  31
- Crystal Oscillator (X1, X2)
  32
- Ip2
  32
- Op3
  32
- JTAG Port Test Signals
  32
- Test Clock (TCK)
  32
- Test Mode Select (TMS)
  32
- Test Data in (TDI)
  32
- Test Data out (TDO)
  32
- Test Reset (TRST)
  32
68000 Bus Operation Description

33
EC000 Core Processor

69
System Operation

91
- MC68306 Address Space
  91
- Table 5-1. MC68306 Memory Map
  92
- Register Description
  93
- System Register
  93
- Timer Vector Register
  94
- Bus Timeout Period Register
  94
- Interrupt Registers
  95
- Interrupt Control Register
  95
- Interrupt Status Register
  96
- I/O Port Registers
  96
- Port Pins Register
  97
- Port Direction Register
  97
- Port Data Register
  98
- Chip Selects
  98
- Chip Select Configuration Registers (High Half)
  99
- Chip Select Configuration Registers (Low Half)
  100
- Table 5-2. Chip Select Match Bits
  101
- DRAM Control Registers
  102
- Figure 5-1. Chip Select Expansion
  102
- Table 5-3. DRAM Address Multiplexer
  103
- DRAM Refresh Register
  104
- DRAM Bank Configuration Register (High Half)
  104
- DRAM Bank Configuration Register (Low Half)
  105
- Table 5-4. DRAM Bank Match Bits
  106
- Automatic DTACK Generation
  107
- Crystal Oscillator
  107
- Figure 5-2. Oscillator Circuit Diagram
  108
Serial Module

109
- Figure 6-1. Simplified Block Diagram
  109
- Module Overview
  110
- Serial Communication Channels a and B
  111
- Baud Rate Generator Logic
  111
- Timer/Counter
  111
- Interrupt Control Logic
  111
- Comparison of Serial Module to MC68681
  112
- Serial Module Signal Definitions
  112
- Channel a Transmitter Serial Data Output (Txda)
  112
- Channel a Receiver Serial Data Input (Rxda)
  113
- Channel B Transmitter Serial Data Output (Txdb)
  113
- Figure 6-2. External and Internal Interface Signals
  113
- Channel B Receiver Serial Data Input (Rxdb)
  114
- Channel a Request-To-Send (RTSA/OP0)
  114
- Rtsa
  114
- Op0
  114
- Channel B Request-To-Send (RTSB/OP1)
  114
- Rtsb
  114
- Op1
  114
- Channel a Clear-To-Send (CTSA/IP0)
  114
- Ctsa
  114
- Ip0
  114
- Operation
  115
- Baud Rate Generator
  115
- Transmitter and Receiver Operating Modes
  115
- Figure 6-3. Baud Rate Generator Block Diagram
  115
- Figure 6-4. Transmitter and Receiver Functional Diagram
  116
- Figure 6-5. Transmitter Timing Diagram
  117
- Transmitter
  118
- Receiver
  119
- FIFO Stack
  119
- Figure 6-6. Receiver Timing Diagram
  119
- Looping Modes
  121
- Automatic Echo Mode
  121
- Local Loopback Mode
  121
- Remote Loopback Mode
  121
- Multidrop Mode
  122
- Figure 6-7. Looping Modes Functional Diagram
  122
- Figure 6-8. Multidrop Mode Timing Diagram
  123
- Counter/Timer
  124
- Counter Mode
  124
- Timer Mode
  124
- Bus Operation
  125
- Read Cycles
  125
- Write Cycles
  125
- Interrupt Acknowledge Cycles
  125
- Register Description and Programming
  125
- Register Description
  125
- Auxiliary Control Register (DUACR)
  126
- Interrupt Status Register (DUISR)
  126
- Interrupt MASK Register (DUIMR)
  126
- Interrupt Vector Register (DUIVR)
  126
- Input Port Register
  126
- Mode Register 1 (DUMR1)
  126
- Figure 6-9. Serial Module Programming Model
  126
- Table 6-1. Pmx and PT Control Bits
  128
- Table 6-2. B/CX Control Bits
  128
- Output Port Control Register (DUOPCR)
  129
- Table 6-3. CMX Control Bits
  129
- Table 6-4. Sbx Control Bits
  130
- Table 6-5. Rcsx Control Bits
  133
- Table 6-6. Tcsx Control Bits
  134
- Table 6-7. Miscx Control Bits
  135
- Table 6-8. Tcx Control Bits
  136
- Table 6-9. Rcx Control Bits
  136
- Table 6-10. Counter/Timer Mode and Source Select Bits
  139
- Count Register Current MSB of Counter (DUCUR)
  141
- Count Register Current LSB of Counter (DUCLR)
  141
- Output Port Data Register (DUOP)
  144
- Start Counter Command Register
  144
- Stop Counter Command Register
  144
- Programming
  145
- Serial Module Initialization
  145
- I/O Driver Example
  145
- Interrupt Handling
  145
- Figure 6-10. Serial Module Programming Flowchart
  146
- Serial Module Initialization Sequence
  151
IEEE 1149.1 Test Access Port

153
Ordering Information and Mechanical Data

185
- Standard Ordering Information
  185
- Pin Assignments
  186
- Package Dimensions
  188

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