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Internally generated IDMA requests are affected by a mechanism supported
to reduce the M68000 core interrupt latency and external bus master arbi-
tration latency (see 3.8.5 Bus Arbitration Logic). The IDMA is forced to relin-
quish the bus when an external bus master requests the bus (BR is asserted)
or when the M68000 core has an unmasked pending interrupt request. In
these cases, the on-chip arbiter sends an internal bus-clear signal to the IDMA.
In response, any operand transfer in progress will be completed, and bus
ownership will be released.
If the core caused the bus to be relinquished, no further IDMA bus cycles
will be started until IPA in the SCR is cleared. If the cause was an external
request, no further IDMA bus cycles will be started while BR remains asserted.
When BR is externally negated, if a transfer request is pending, the IDMA
will arbitrate for the bus and continue normal operation.
3.1. 7 Bus Exceptions
In any computer system, the possibility always exists that an error will occur
during a bus cycle due to a hardware failure, random noise, or an improper
access. When an asynchronous bus structure, such as that supported by the
M68000 is used, it is easy to make provisions allowing a bus master to detect
and respond to errors during a bus cycle. The IDMA recognizes the same
bus exceptions as the M68000 core: reset, bus error, halt, and retry.
NOTE
These exceptions also apply to the SOMA channels except that the
reporting method is different. See 4.5 SERIAL COMMUNICATION
CONTROLLERS (SCCsl for further details.
3.1.7.1 RESET.
Upon an external reset, the IDMA channel immediately aborts the
channel operation, returns to the idle state, and clears CSR and CMR (in-
cluding the STR bit). If a bus cycle is in progress when reset is detected, the
cycle is systematically terminated, the control and address/data pins are
three-stated, and bus ownership is released. The IDMA can also be reset by
RST in the CMR.
3.1.7.2 BUS ERROR. When a fatal error occurs during a bus cycle, a bus error
exception is used to abort the cycle and systematically terminate that chan-
nel's operation. The IDMA terminates the current operation, signals an error
in the CSR, and generates a maskable interrupt. The IDMA clears STR and
3-16
MC68302 USER'S MANUAL
MOTOROLA
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