Interrupt Configuration Register; Table 19-23 Interrupt Configuration Register Description - Motorola DragonBall MC9328MX1 Reference Manual

19.4.15 Interrupt Configuration Register

The Interrupt Configuration Register is used to configure the interrupt conditions.
LCDICR
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Table 19-23. Interrupt Configuration Register Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–3
INTSYN Interrupt Source—Determines if an interrupt flag is
Bit 2 set during last data/first data of frame loading or on
last data/first data of frame output to the LCD panel.
Note: There is a latency between loading the
last/first data of frame to output to LCD panel.
Reserved Reserved—This bit is reserved and should read 0.
Bit 1
INTCON Interrupt Condition—Determines if an interrupt
Bit 0 condition is set at the beginning or the end of frame
condition.
MOTOROLA
Interrupt Configuration Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
r r r r
0 0 0 0
Description
LCD Controller
24 23 22 21 20
r r r r
0 0 0 0 0
0X0000
8 7 6 5 4
r r r r
0 0 0 0 0
0x0000
0 = Interrupt flag is set on loading the last
data/first data of frame from memory
1 = Interrupt flag is set on output of the last
data/first data of frame to LCD panel
0 = Interrupt flag is set when the End of
Frame (EOF) is reached
1 = Interrupt flag is set when the Beginning
of Frame (BOF) is reached
Programming Model
Addr
0x00205038
19 18 17 16
r r r r
0 0 0
3 2 1
INT INT
SYN CON
r r rw r rw
0 0 0
Settings
19-35
r
0
0
0