Instruction Cache Write; Restrictions; Instruction Cache Coherency; Updating Code And Memory Region Attributes - Motorola MPC823e Reference Manual

Instruction Cache
LRU—Least-Recently Used
This bit indicates that the entry is aged or least recently used.
Bit 24—When set, way 3 is more recently used than way 2.
Bit 25—When set, way 3 is more recently used than way 1.
Bit 26—When set, way 3 is more recently used than way 0.
Bit 27—When set, way 2 is more recently used than way 1.
Bit 28—When set, way 2 is more recently used than way 0.
Bit 29—When set, way 1 is more recently used than way 0.

9.4.7 Instruction Cache Write

Instruction cache write is only enabled when the MPC823e is in test mode.

9.5 RESTRICTIONS

Zero wait state devices that are placed on the internal bus are considered to be in the
cache-inhibited memory region and the hardware correct operation trusts the software to
follow the exact steps mentioned in Section 9.7 Updating Code And Memory Region
Attributes. It is not recommended that you perform LOAD & LOCK from zero wait state
devices that are placed on the internal bus, especially since it is not guaranteed that the data
will be fetched from the instruction cache. In most cases, it is fetched from the device, but
found in the instruction cache.

9.6 INSTRUCTION CACHE COHERENCY

Cache coherency in a multiprocessor environment is maintained by the software and
supported by the invalidation mechanism as described above. All instruction storage is
considered to be coherent, not required, mode.

9.7 UPDATING CODE AND MEMORY REGION ATTRIBUTES

To update the code or change the programming of the memory regions in the chip-select
logic, follow these steps:
1. Update the code and change the memory region programming in the chip-select logic.
2. Execute the sync instruction to ensure that the update/change operation has finished.
3. Unlock all locked lines that contain code that was updated.
4. Invalidate all lines that contain code that was updated.
5. Execute the isync instruction.

9.8 RESET SEQUENCE

To simplify the debug task of the system, the instruction cache is only disabled during
hardware reset (IC_CST
the instruction cache prior to the event that asserts the reset. To ensure proper operation of
the instruction cache after reset, the UNLOCK ALL, INVALIDATE ALL, and
INSTRUCTION CACHE ENABLE commands must be executed.
9-14
= 0). This feature enables you to investigate the exact state of
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