Page-Hit Cpu Byte-Write Cycle For 8-Bit Sdram (Cas Latency = 1); Figure 19-20 Page-Hit Cpu Byte-Write Cycle For 8-Bit Sdram Timing Diagram - Motorola MC68VZ328 User Manual

AC Electrical Characteristics
19.3.19 Page-Hit CPU Byte-Write Cycle for 8-Bit SDRAM (CAS
Latency = 1)
Figure 19-20 shows the timing diagram for the page-hit SDRAM CPU byte-write cycle for 8-bit SDRAM.
The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed
information about the operation of individual signals can be found in both Chapter 8, "LCD Controller,"
and Chapter 7, "DRAM Controller."
S0
SDCLK
SCKEN
A[16:1]/MD[15:0]
SDA10
CS
RAS
CAS
D[15:0]
WE
DQM
DTACK
Figure 19-20. Page-Hit CPU Byte-Write Cycle for 8-Bit SDRAM Timing Diagram
19-24
S1 S2 S3 S4 S5 S6
Col
Upper Byte Lower Byte
12
Write
Command
MC68VZ328 User's Manual
S7
13