Table of Contents
Advertisement
Because the PowerPC architecture can be applied to such a wide variety of
implementations, instruction timing varies among PowerPC processors.
For a detailed discussion of instruction timing with examples and a table of latencies for
each execution unit, see Chapter 6, "Instruction Timing."
1.10 Power Management
The MPC750 provides four power modes, selectable by setting the appropriate control bits
in the MSR and HIDO registers. The four power modes are as follows:
•
Full-power-This is the default power state of the MPC750. The MPC750 is fully
powered and the internal functional units are operating at the full processor clock
speed. If the dynamic power management mode is enabled, functional units that are
idle will automatically enter a low-power state without affecting performance,
software execution, or external hardware.
•
Doze-All the functional units of the MPC750 are disabled except for the time
base/decrementer registers and the bus snooping logic. When the processor is in
doze mode, an external asynchronous interrupt, a system management interrupt, a
decrementer exception, a hard or soft reset, or machine check brings the MPC750
into the full-power state. The MPC750 in doze mode maintains the PLL in a fully
powered state and locked to the system external clock input (SYSCLK) so a
transition to the full-power state takes only a few processor clock cycles.
•
N ap-The nap mode further reduces power consumption by disabling bus snooping,
leaving only the time base register and the PLL in a powered state. The MPC750
returns to the full-power state upon receipt of an external asynchronous interrupt, a
system management interrupt, a decrementer exception, a hard or soft reset, or a
machine check input (MCP). A return to full-power state from a nap state takes only
a few processor clock cycles. When the processor is in nap mode, if QACK is
negated, the processor is put in doze mode to support snooping.
•
Sleep-Sleep mode minimizes power consumption by disabling all internal
functional units, after which external system logic may disable the PLL and
SYSCLK. Returning the MPC750 to the full-power state requires the enabling of the
PLL and SYSCLK, followed by the assertion of an external asynchronous interrupt,
a system management interrupt, a hard or soft reset, or a machine check input (MCP)
signal after the time required to re10ck the PLL.
Chapter 10, "Power and Thermal Management," provides information about power saving
and thermal management modes for the MPC750.
1-36
MPC750 RISC Microprocessor User's Manual
Advertisement
Table of Contents
