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•
If a receive interrupt occurs when the HROE is cleared, the regular receive-data interrupt vector is
generated.
The HROE bit is cleared by reading the HCSR register with the HROE bit set, followed by reading the
HRX FIFO. The HROE bit is cleared by hardware, software, and SHI individual resets, and also during
the stop state.
10.3.8.18 Host Bus Error (HBER)—Bit 21
When the read-only status bit HBER is set, it indicates that an SHI bus error occurred when operating as
a master (HMST bit is set).
2
•
In I
C mode, the HBER bit is set if the transmitter does not receive an acknowledge after a byte is
transferred; then a stop event is generated and transmission is suspended.
•
In SPI mode, the HBER bit is set if the SS line is asserted; then the transmission is suspended at
the end of transmission of the current word.
The HBER bit is cleared only by hardware, software, and SHI individual resets, and also during the stop
state.
10.3.8.19 HCSR Host Busy (HBUSY)—Bit 22
The read-only status bit HBUSY indicates that the I
itself is busy (when in the SPI mode).
•
When operating in I
HBUSY bit remains set until a stop event is detected.
•
When operating in the slave SPI mode, the HBUSY bit is set while the SS line is asserted.
•
When operating in the master SPI mode, the HBUSY bit is set if the HTX register is not empty or
if the IOSR register is not empty.
The HBUSY bit is cleared otherwise. The HBUSY bit is cleared by hardware, software, and SHI individual
resets, and also during the stop state.
10.4
Characteristics Of The SPI Bus
The SPI bus consists of two serial data lines (MISO, MOSI), a clock line (SCK) and a Slave Select line
(SS). During an SPI transfer, a byte is shifted out one data pin while a different byte is simultaneously
shifted in through a second data pin. It can be viewed as two 8-bit shift registers connected together in a
circular manner, with one shift register on the master side and the other shift register on the slave side.
Thus the data bytes in the master device and slave device are exchanged.
The MISO and MOSI data pins are used for transmitting and receiving serial data.
•
When the SPI is configured as a master, MISO is the master data input line, and MOSI is the master
data output line.
•
When the SPI is configured as a slave, MISO is the slave data output line, and MOSI is the slave
data input line.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
2
C mode, the HBUSY bit is set after the SHI detects a start event, and the
2
C bus is busy (when in the I
Serial Host Interface (SHI, SHI_1)
2
C mode) or that the SHI
10-17
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