Class: Class Register; Cls: Cache Line Size; Mlt: Master Latency Timer Register; Hdr: Header Register - Intel 460GX Software Developer’s Manual

WXB Hot-Plug
Bits
7:0
8.1.7

CLASS: Class Register

Address Offset:
Default Value:
This register contains the Class Code for the IHPC, specifying the device function. Writes to this
register will have no effect.
Bits
23:16
15:8
7:0
8.1.8

CLS: Cache Line Size

Address Offset:
Default Value:
See PCI Specification, Rev. 2.2.
8.1.9

MLT: Master Latency Timer Register

Address Offset:
Default Value:
See PCI Specification, Rev. 2.2. This register is not applicable to the IHPC's within the WXB.
8.1.10

HDR: Header Register

Address Offset:
Default Value:
This register identifies the header layout of the configuration space. Writes to this register will have
no effect.
8-6
Description
Revision Identification Number
This is an 8-bit value that indicates the revision identification number for the IHPC
WXB A Steppings: Hardwired Value = 00h
WXB B0 Step: Hardwired Value = 01h
09 – 0Bh
080400h
Description
Base Class
This field indicates the general device category. The IHPC is a Base System Peripheral.
Hardwired Value = 08h.
Sub-Class
This field qualifies the Base Class, providing a more detailed specification of the device
function. For the IHPC this field indicates a Generic PCI Hot-Plug Controller. Hardwired
Value = 04h.
Register-level Programming Interface
This field identifies a specific programming interface (if any), that device independent
software can use to interact with the device. The Interface is not defined. Hardwired
Value = 00h.
0Ch
00h
0Dh
00h
0Eh
00h
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Intel® 460GX Chipset Software Developer's Manual
24 bits
Read-Only
8 bits
Read/Write
8 bits
Read/Write
8 bits
Read-Only