Cls-Cache Line Size Register; Mtxt2-Master Latency Timer Register; Hdr2-Header Type Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.8.7 CLS—Cache Line Size Register
The IGD does not support this register as a PCI slave.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
7:0
2.8.8 MTXT2—Master Latency Timer Register
The IGD does not support the programmability of the master latency timer because it
does not perform bursts.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
7:0
2.8.9 HDR2—Header Type Register
This register contains the Header Type of the IGD.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
7
6:0
Datasheet, Volume 2
0/2/0/PCI
Ch
00h
RO
8 bits
Reset RST/
Attr
Value PWR
RO 00h Uncore
0/2/0/PCI
Dh
00h
RO
8 bits
Reset RST/
Attr
Value PWR
RO 00h Uncore
0/2/0/PCI
Eh
00h
RO
8 bits
Reset RST/
Attr
Value PWR
RO 0b Uncore
RO 00h Uncore
Description
Cache Line Size (CLS)
This field is hardwired to 0s. The IGD as a PCI compliant master
does not use the Memory Write and Invalidate command and, in
general, does not perform operations based on cache line size.
Description
Master Latency Timer Count Value (MTXTCV)
Hardwired to 0s.
Description
Multi Function Status (MFUNC)
This bit indicates if the device is a Multi-Function Device. The Value
of this register is hardwired to 0; the processor graphics is a single
function.
Header Code (H)
This is a 7-bit value that indicates the Header Code for the IGD.
This code has the value 00h, indicating a type 0 configuration
space format.
133