Timer 2 Control Register - Intel 80C186EA User Manual

Register Name:
Register Mnemonic:
Register Function:
15
I
E I
N N N
H T
Bit
Bit Name
Mnemonic
EN Enable
INH Inhibit
INT Interrupt
MC Maximum
Count
CONT Continuous
Mode
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Timer 2 Control Register

T2CON
Defines Timer 2 operation.
Reset
State
0 Set to enable the timer. This bit can be written
only when the INH bit is set.
X Set to enable writes to the EN bit. Clear to
ignore writes to the EN bit. The INH bit is not
stored; it always reads as zero.
X Set to generate an interrupt request when the
Count register equals a Maximum Count
register. Clear to disable interrupt requests.
X This bit is set when the counter reaches a
maximum count. The MC bit must be cleared
by writing to the Timer Control register. This
is not done automatically. If MC is clear, the
counter has not reached a maximum count.
X Set to cause the timer to run continuously.
Clear to disable the counter (clear the EN bit)
after each counting sequence.
Figure 9-6. Timer 2 Control Register
TIMER/COUNTER UNIT
M
C
Function
0
C
O
N
T
A1298-0A
9-9