INTEL 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - VOLUME 2 01-2011 Manuals

Table of Contents

• • 2

    Datasheet, Volume
    • 3

      Table of Contents
    • 10

      Revision History

• 11

  1 Introduction

• 13

  2 Processor Configuration Registers

  • 13

    Register Terminology
  • 13

    Register Attributes and Terminology
  • 14

    PCI Devices and Functions On Processor
  • 14

    Register Attribute Modifiers
  • 15

    System Address Map
  • 17

    System Address Range Example
    • 18

      Legacy Address Range
      • 18

        DOS Range (0H-9_Ffffh)
  • 18

    DOS Legacy Address Range
    • 19

      Legacy Video Area (A_0000H-B_Ffffh)
    • 20

      PAM (C_0000H-F_Ffffh)
    • 20

      Main Memory Address Range (1 MB - TOLUD)
  • 20

    Main Memory Address Range
    • 21

      ISA Hole (15 MB-16 MB)
    • 21

      Tseg
    • 21

      Protected Memory Range (PMR) - (Programmable)
    • 22

      DRAM Protected Range (DPR)
    • 22

      Pre-Allocated Memory
    • 23

      GFX Stolen Spaces
    • 23

      Me Uma
    • 23

      PCI Memory Address Range (TOLUD - 4 GB)
  • 24

    PCI Memory Address Range
    • 25

      APIC Configuration Space (Fec0_0000H-Fecf_Ffffh)
    • 25

      HSEG (Feda_0000H-Fedb_Ffffh)
    • 25

      MSI Interrupt Memory Space (Fee0_0000H-Feef_Ffffh)
    • 25

      High BIOS Area
    • 26

      Main Memory Address Space (4 GB to TOUUD)
      • 27

        Memory Re-Claim Background
      • 27

        Indirect Accesses to MCHBAR Registers
      • 28

        Memory Remapping
      • 28

        Hardware Remap Algorithm
      • 28

        Programming Model
  • 29

    Case 1: Less Than 4 GB of Physical Memory (No Remap)
  • 30

    Case 2: Greater Than 4 GB of Physical Memory
    • 32

      PCI Express* Configuration Address Space
    • 33

      PCI Express* Graphics Attach (PEG)
    • 34

      Graphics Memory Address Ranges
      • 34

        IOBAR Mapped Access to Device 2 MMIO Space
      • 34

        Trusted Graphics Ranges
    • 35

      System Management Mode (SMM)
    • 35

      SMM and VGA Access Through GTT TLB
    • 35

      ME Stolen Memory Accesses
  • 35

    SMM Regions
    • 36

      I/O Address Space
      • 36

        PCI Express* I/O Address Mapping
    • 37

      MCTP and KVM Flows
    • 37

      Decode Rules and Cross-Bridge Address Mapping
      • 37

        DMI Interface Decode Rules
  • 39

    Example: DMI Upstream VC0 Memory Map
    • 40

      PCI Express* Interface Decode Rules
    • 41

      Legacy VGA and I/O Range Decode Rules
  • 41

    PEG Upstream VC0 Memory Map
  • 42

    IGD Frame Buffer Accesses
  • 42

    IGD VGA I/O Mapping
  • 43

    VGA and MDA I/O Transaction Mapping
  • 45

    Processor Register Introduction
    • 46

      I/O Mapped Registers
  • 46

    PCI Device 0 Function 0 Configuration Space
  • 46

    PCI Device 0, Function 0 Register Address Map
    • 48

      VID-Vendor Identification Register
    • 48

      DID-Device Identification Register
    • 49

      PCICMD-PCI Command Register
    • 50

      PCISTS-PCI Status Register
    • 52

      Rid-Revision Identification Register
    • 53

      CC-Class Code Register
    • 53

      Hdr-Header Type Register
    • 54

      Svid-Subsystem Vendor Identification Register
  • 54

    Sid-Subsystem Identification Register
  • 55

    PXPEPBAR-PCI Express Egress Port Base Address Register
  • 56

    Mchbar-Host Memory Mapped Register Range Base Register
  • 57

    GGC-GMCH Graphics Control Register Register
  • 59

    Deven-Device Enable Register
  • 60

    PCIEXBAR-PCI Express Register Range Base Address Register
  • 62

    Dmibar-Root Complex Register Range Base Address Register
  • 63

    Pam0-Programmable Attribute Map 0 Register
  • 64

    Pam1-Programmable Attribute Map 1 Register
  • 65

    Pam2-Programmable Attribute Map 2 Register
  • 66

    Pam3-Programmable Attribute Map 3 Register
  • 67

    Pam4-Programmable Attribute Map 4 Register
  • 68

    Pam5-Programmable Attribute Map 5 Register
  • 69

    Pam6-Programmable Attribute Map 6 Register
  • 70

    Lac-Legacy Access Control Register
  • 74

    Remapbase-Remap Base Address Register
  • 74

    Remaplimit-Remap Limit Address Register
  • 75

    Tom-Top of Memory Register
  • 76

    Touud-Top of Upper Usable DRAM Register
  • 77

    Bdsm-Base Data of Stolen Memory Register
  • 77

    Bgsm-Base of GTT Stolen Memory Register
  • 78

    G Memory Base Register
  • 78

    Tolud-Top of Low Usable DRAM Register
  • 79

    Skpd-Scratchpad Data Register
  • 80

    Capid0_A-Capabilities a Register

• 82

  PCI Device 1 Function 0-2 Configuration Space

  • 82

    PCI Device 1, Function 0-2 Configuration Register Address Map
  • 84

    Vid1-Vendor Identification Register
  • 84

    Did1-Device Identification Register
  • 85

    PCICMD1-PCI Command Register
  • 87

    PCISTS1-PCI Status Register
  • 89

    Rid1-Revision Identification Register
  • 89

    Cc1-Class Code Register
  • 90

    Cl1-Cache Line Size Register
  • 90

    Hdr1-Header Type Register
  • 90

    Pbusn1-Primary Bus Number Register
  • 91

    Sbusn1-Secondary Bus Number Register
  • 91

    Subusn1-Subordinate Bus Number Register
  • 92

    IOBASE1-I/O Base Address Register
  • 92

    IOLIMIT1-I/O Limit Address Register
  • 93

    Ssts1-Secondary Status Register
  • 94

    Mbase1-Memory Base Address Register
  • 95

    Mlimit1-Memory Limit Address Register
  • 96

    Pmbase1-Prefetchable Memory Base Address Register
  • 97

    Pmlimit1-Prefetchable Memory Limit Address Register
  • 98

    Pmbaseu1-Prefetchable Memory Base Address Upper Register
  • 98

    Pmlimitu1-Prefetchable Memory Limit Address Upper Register
  • 99

    Capptr1-Capabilities Pointer Register
  • 99

    Intrline1-Interrupt Line Register
  • 100

    Intrpin1-Interrupt Pin Register
  • 100

    Bctrl1-Bridge Control Register
  • 102

    Pm_Capid1-Power Management Capabilities Register
  • 103

    Pm_Cs1-Power Management Control/Status Register
  • 104

    Ss_Capid-Subsystem ID and Vendor ID Capabilities Register
  • 105

    Ss-Subsystem ID and Subsystem Vendor ID Register
    • 105

      Msi_Capid-Message Signaled Interrupts Capability ID Register
    • 106

      MC-Message Control Register
    • 107

      Ma-Message Address Register
    • 107

      MD-Message Data Register
    • 107

      PEG_CAPL-PCI Express-G Capability List Register
    • 108

      PEG_CAP-PCI Express-G Capabilities Register
    • 108

      Dcap-Device Capabilities Register
    • 109

      Dctl-Device Control Register
    • 110

      Dsts-Device Status Register
    • 111

      Lctl-Link Control Register
    • 113

      Lsts-Link Status Register
    • 114

      Slotcap-Slot Capabilities Register
    • 116

      Slotctl-Slot Control Register
    • 118

      Slotsts-Slot Status Register
    • 120

      Rctl-Root Control Register
    • 120

      Lctl2-Link Control 2 Register
  • 123

    PCI Device 1 Function 0-2 Extended Configuration
    • 123

      Pvccap1-Port VC Capability Register 1
  • 123

    PCI Device 1 Function 0-2 Extended Configuration Register Address Map
    • 124

      Pvccap2-Port VC Capability Register 2
    • 124

      Pvcctl-Port VC Control Register
    • 125

      VC0RCAP-VC0 Resource Capability Register
    • 126

      VC0RCTL-VC0 Resource Control Register
    • 127

      VC0RSTS-VC0 Resource Status Register
    • 127

      PEG_TC-PCI Express Completion Time-Out Register
  • 128

    PCI Device 2 Configuration Space
  • 128

    PCI Device 2 Configuration Register Address Map
    • 129

      Vid2-Vendor Identification Register
    • 129

      Did2-Device Identification Register
    • 130

      PCICMD2-PCI Command Register
    • 131

      PCISTS2-PCI Status Register
    • 132

      Rid2-Revision Identification Register
    • 132

      CC-Class Code Register
    • 133

      Cls-Cache Line Size Register
    • 133

      Mtxt2-Master Latency Timer Register
    • 133

      Hdr2-Header Type Register
    • 134

      Gttmmadr-Graphics Translation Table, Memory Mapped Range Address Register
    • 135

      Gmadr-Graphics Memory Range Address Register
    • 136

      IOBAR-I/O Base Address Register
    • 136

      Svid2-Subsystem Vendor Identification Register
    • 137

      Sid2-Subsystem Identification Register
    • 137

      Romadr-Video BIOS ROM Base Address Register
    • 137

      Intrpin-Interrupt Pin Register
    • 138

      Mingnt-Minimum Grant Register
    • 138

      Maxlat-Maximum Latency Register
    • 139

      Msac-Multi Size Aperture Control Register
  • 140

    Device 2 IO
    • 140

      INDEX-MMIO Address Register
    • 140

      DATA-MMIO Data Register
  • 141

    PCI Device 6
    • 141

      PCI Device 6 Register Address Map
    • 143

      Did6-Device Identification Register
    • 143

      Vid6-Vendor Identification Register
    • 144

      PCICMD6-PCI Command Register
    • 146

      PCISTS6-PCI Status Register
    • 148

      Cc6-Class Code Register
    • 148

      Rid6-Revision Identification Register
    • 149

      Cl6-Cache Line Size Register
  • 149

    Hdr6-Header Type Register
  • 149

    Pbusn6-Primary Bus Number Register
  • 150

    Sbusn6-Secondary Bus Number Register
  • 150

    Subusn6-Subordinate Bus Number Register
  • 151

    IOBASE6-I/O Base Address Register
  • 151

    IOLIMIT6-I/O Limit Address Register
  • 152

    Ssts6-Secondary Status Register
  • 153

    Mbase6-Memory Base Address Register
  • 154

    Mlimit6-Memory Limit Address Register
  • 155

    Pmbase6-Prefetchable Memory Base Address Register
  • 156

    Pmlimit6-Prefetchable Memory Limit Address Register
  • 157

    Pmbaseu6-Prefetchable Memory Base Address Upper Register
  • 158

    Pmlimitu6-Prefetchable Memory Limit Address Upper Register
  • 158

    Capptr6-Capabilities Pointer Register
  • 159

    Intrline6-Interrupt Line Register
  • 159

    Intrpin6-Interrupt Pin Register
  • 160

    Bctrl6-Bridge Control Register
  • 162

    Pm_Capid6-Power Management Capabilities Register
  • 163

    Pm_Cs6-Power Management Control/Status Register
  • 164

    Ss_Capid-Subsystem ID and Vendor ID Capabilities Register
  • 165

    Ss-Subsystem ID and Subsystem Vendor ID Register
  • 165

    Msi_Capid-Message Signaled Interrupts Capability ID Register
  • 166

    MC-Message Control Register
  • 167

    Ma-Message Address Register
  • 167

    MD-Message Data Register
  • 167

    PEG_CAPL-PCI Express-G Capability List Register
  • 168

    PEG_CAP-PCI Express-G Capabilities Register
  • 168

    Dcap-Device Capabilities Register
  • 169

    Dctl-Device Control Register
  • 170

    Dsts-Device Status Register
  • 171

    Lctl-Link Control Register
  • 173

    Lsts-Link Status Register
  • 174

    Slotcap-Slot Capabilities Register
  • 176

    Slotctl-Slot Control Register
  • 178

    Slotsts-Slot Status Register
  • 179

    Rctl-Root Control Register

• 180

  PCI Device 6 Extended Configuration

  • 180

    Pvccap1-Port VC Capability Register 1
  • 180

    PCI Device 6 Extended Configuration Register Address Map
  • 181

    Pvccap2-Port VC Capability Register 2
  • 181

    Pvcctl-Port VC Control Register
  • 182

    VC0RCAP-VC0 Resource Capability Register
  • 183

    VC0RCTL-VC0 Resource Control Register
  • 184

    VC0RSTS-VC0 Resource Status Register

• 185

  Dmibar

  • 186

    DMIVCECH-DMI Virtual Channel Enhanced Capability Register
  • 187

    DMIPVCCAP1-DMI Port VC Capability Register 1
  • 187

    DMIPVCCAP2-DMI Port VC Capability Register 2
  • 188

    DMIPVCCTL-DMI Port VC Control Register
  • 188

    DMIVC0RCAP-DMI VC0 Resource Capability Register
  • 189

    DMIVC0RCTL-DMI VC0 Resource Control Register
  • 190

    DMIVC0RSTS-DMI VC0 Resource Status Register
  • 190

    DMIVC1RCAP-DMI VC1 Resource Capability Register
  • 191

    DMIVC1RCTL-DMI VC1 Resource Control Register
  • 192

    DMIVC1RSTS-DMI VC1 Resource Status Register
  • 192

    DMIVCPRCAP-DMI Vcp Resource Capability Register
  • 193

    DMIVCPRCTL-DMI Vcp Resource Control Register
    • 194

      DMIVCPRSTS-DMI Vcp Resource Status Register
    • 195

      DMIESD-DMI Element Self Description Register
    • 196

      DMILE1D-DMI Link Entry 1 Description Register
    • 196

      DMILE1A-DMI Link Entry 1 Address Register
    • 197

      DMILE2D-DMI Link Entry 2 Description Register
    • 197

      DMILE2A-DMI Link Entry 2 Address Register
    • 198

      Lcap-Link Capabilities Register
    • 199

      Lctl-Link Control Register
    • 200

      LSTS-DMI Link Status Register
    • 201

      Lctl2-Link Control 2 Register
    • 203

      Lsts2-Link Status 2 Register
  • 204

    MCHBAR Registers in Memory Controller - Channel 0
    • 204

      Pm_Pdwn_Config_C0-Power-Down Configuration Register
  • 204

    MCHBAR Registers in Memory Controller - Channel 0 Register Address Map
    • 205

      Tc_Rfp_C0-Refresh Parameters Register
    • 205

      Tc_Rftp_C0-Refresh Parameters Register
  • 206

    MCHBAR Registers in Memory Controller - Channel 1
    • 206

      Pm_Pdwn_Config_C1-Power-Down Configuration Register
  • 206

    MCHBAR Registers in Memory Controller - Channel 1 Register Address Map
    • 207

      Tc_Rfp_C1-Refresh Parameters Register
    • 207

      Tc_Rftp_C1-Refresh Timing Parameters Register
  • 208

    MCHBAR Registers in Memory Controller - Integrated Memory Peripheral Hub (IMPH)
    • 208

      Crdtctl3-Credit Control 3 Register
  • 208

    MCHBAR Registers in Memory Controller - Integrated Memory Peripheral Hub
  • 209

    MCHBAR Registers in Memory Controller - Common
    • 209

      Mad_Chnl-Address Decoder Channel Configuration Register
  • 209

    MCHBAR Registers in Memory Controller - Common Register Address Map
    • 210

      Mad_Dimm_Ch0-Address Decode Channel 0 Register
    • 211

      Mad_Dimm_Ch1 - Address Decode Channel 1 Register
    • 212

      Pm_Sref_Config-Self Refresh Configuration Register
  • 213

    Memory Controller MMIO Registers Broadcast Group
    • 213

      Pm_Pdwn_Config-Power-Down Configuration Register
  • 213

    Memory Controller MMIO Registers Broadcast Group Register Address Map
    • 214

      Pm_Cmd_Pwr-Power Management Command Power Register
    • 214

      Pm_Bw_Limit_Config-Bw Limit Configuration Register
  • 215

    Integrated Graphics Vtd Remapping Engine Registers
  • 215

    Integrated Graphics Vtd Remapping Engine Register Address Map
    • 216

      Ver_Reg-Version Register
    • 217

      Cap_Reg-Capability Register
    • 220

      Ecap_Reg-Extended Capability Register
    • 222

      Gcmd_Reg-Global Command Register
    • 225

      Gsts_Reg-Global Status Register
    • 226

      Rtaddr_Reg-Root-Entry Table Address Register
    • 227

      Ccmd_Reg-Context Command Register
    • 229

      Fsts_Reg-Fault Status Register
    • 231

      Fectl_Reg-Fault Event Control Register
    • 232

      Fedata_Reg-Fault Event Data Register
    • 232

      Feaddr_Reg-Fault Event Address Register
    • 232

      Feuaddr_Reg-Fault Event Upper Address Register
    • 233

      Aflog_Reg-Advanced Fault Log Register
    • 234

      Pmen_Reg-Protected Memory Enable Register
    • 235

      Plmbase_Reg-Protected Low-Memory Base Register
    • 236

      Plmlimit_Reg-Protected Low-Memory Limit Register
    • 237

      Phmbase_Reg-Protected High-Memory Base Register
    • 238

      Phmlimit_Reg-Protected High-Memory Limit Register
    • 239

      Iqh_Reg-Invalidation Queue Head Register
    • 239

      Iqt_Reg-Invalidation Queue Tail Register
    • 240

      Iqa_Reg-Invalidation Queue Address Register
    • 240

      Ics_Reg-Invalidation Completion Status Register
    • 241

      Iectl_Reg-Invalidation Event Control Register
    • 242

      Iedata_Reg-Invalidation Event Data Register
  • 242

    Ieuaddr_Reg-Invalidation Event Upper Address Register
  • 243

    Irta_Reg-Interrupt Remapping Table Address Register
  • 244

    Iva_Reg-Invalidate Address Register
  • 245

    IOTLB_REG-IOTLB Invalidate Register
  • 247

    Frcdl_Reg-Fault Recording Low Register
  • 248

    Frcdh_Reg-Fault Recording High Register
  • 249

    VTPOLICY-DMA Remap Engine Policy Control Register

• 250

  PCU MCHBAR Registers

  • 250

    PCU MCHBAR Register Address Map
  • 251

    Mem_Trml_Estimation_Config-Memory Thermal Estimation Configuration Register
  • 252

    Mem_Trml_Thresholds_Config-Memory Thermal Thresholds Configuration Register
  • 253

    Mem_Trml_Status_Report-Memory Thermal Status Report Register
  • 254

    Mem_Trml_Temperature_Report-Memory Thermal Temperature Report Register
  • 254

    Mem_Trml_Interrupt-Memory Thermal Interrupt Register
  • 255

    GT_PERF_STATUS-GT Performance Status Register
  • 255

    RP_STATE_CAP-RP State Capability Register
  • 256

    Sskpd-Sticky Scratchpad Data Register

• 258

  Pxpepbar

  • 258

    EPVC0RCTL-EP VC 0 Resource Control Register

• 259

  Default PEG/DMI Vtd Remapping Engine Registers

  • 259

    Default PEG/DMI Vtd Remapping Engine Register Address Map
  • 260

    Ver_Reg-Version Register
  • 261

    Cap_Reg-Capability Register
  • 264

    Ecap_Reg-Extended Capability Register
  • 266

    Gcmd_Reg-Global Command Register
  • 269

    Gsts_Reg-Global Status Register
  • 270

    Rtaddr_Reg-Root-Entry Table Address Register
  • 271

    Ccmd_Reg-Context Command Register
  • 273

    Fsts_Reg-Fault Status Register
  • 275

    Fectl_Reg-Fault Event Control Register
  • 276

    Fedata_Reg-Fault Event Data Register
  • 276

    Feaddr_Reg-Fault Event Address Register
  • 276

    Feuaddr_Reg-Fault Event Upper Address Register
  • 277

    Aflog_Reg-Advanced Fault Log Register
  • 278

    Pmen_Reg-Protected Memory Enable Register
  • 279

    Plmbase_Reg-Protected Low-Memory Base Register
  • 280

    Plmlimit_Reg-Protected Low-Memory Limit Register
  • 281

    Phmbase_Reg-Protected High-Memory Base Register
  • 282

    Phmlimit_Reg-Protected High-Memory Limit Register
  • 283

    Iqh_Reg-Invalidation Queue Head Register
  • 283

    Eg-Invalidation Queue Tail Register
  • 284

    Iqa_Reg-Invalidation Queue Address Register
  • 284

    Ics_Reg-Invalidation Completion Status Register
  • 285

    Iectl_Reg-Invalidation Event Control Register
  • 286

    Iedata_Reg-Invalidation Event Data Register
  • 286

    Ieaddr_Reg-Invalidation Event Address Register
  • 287

    Ieuaddr_Reg-Invalidation Event Upper Address Register
  • 287

    Irta_Reg-Interrupt Remapping Table Address Register
  • 288

    Iva_Reg-Invalidate Address Register
  • 289

    IOTLB_REG-IOTLB Invalidate Register