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2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - VOLUME 2 01-2011
INTEL 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - VOLUME 2 01-2011 Manuals
Manuals and User Guides for INTEL 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - VOLUME 2 01-2011. We have
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INTEL 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - VOLUME 2 01-2011 manual available for free PDF download: Datasheet
INTEL 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - VOLUME 2 01-2011 Datasheet (290 pages)
Brand:
INTEL
| Category:
Computer Hardware
| Size: 4.43 MB
Table of Contents
Datasheet, Volume
2
Table of Contents
3
Revision History
10
1 Introduction
11
2 Processor Configuration Registers
13
Register Terminology
13
Register Attributes and Terminology
13
PCI Devices and Functions on Processor
14
Register Attribute Modifiers
14
System Address Map
15
System Address Range Example
17
Legacy Address Range
18
DOS Range (0H-9_Ffffh)
18
DOS Legacy Address Range
18
Legacy Video Area (A_0000H-B_Ffffh)
19
PAM (C_0000H-F_Ffffh)
20
Main Memory Address Range (1 MB - TOLUD)
20
Main Memory Address Range
20
ISA Hole (15 MB-16 MB)
21
Tseg
21
Protected Memory Range (PMR) - (Programmable)
21
DRAM Protected Range (DPR)
22
Pre-Allocated Memory
22
GFX Stolen Spaces
23
Me Uma
23
PCI Memory Address Range (TOLUD - 4 GB)
23
PCI Memory Address Range
24
APIC Configuration Space (Fec0_0000H-Fecf_Ffffh)
25
HSEG (Feda_0000H-Fedb_Ffffh)
25
MSI Interrupt Memory Space (Fee0_0000H-Feef_Ffffh)
25
High BIOS Area
25
Main Memory Address Space (4 GB to TOUUD)
26
Indirect Accesses to MCHBAR Registers
27
Memory Re-Claim Background
27
Hardware Remap Algorithm
28
Memory Remapping
28
Programming Model
28
Case 1: Less than 4 GB of Physical Memory (no Remap)
29
Case 2: Greater than 4 GB of Physical Memory
30
PCI Express* Configuration Address Space
32
PCI Express* Graphics Attach (PEG)
33
Graphics Memory Address Ranges
34
IOBAR Mapped Access to Device 2 MMIO Space
34
Trusted Graphics Ranges
34
ME Stolen Memory Accesses
35
SMM and VGA Access through GTT TLB
35
System Management Mode (SMM)
35
SMM Regions
35
I/O Address Space
36
PCI Express* I/O Address Mapping
36
Decode Rules and Cross-Bridge Address Mapping
37
DMI Interface Decode Rules
37
MCTP and KVM Flows
37
Example: DMI Upstream VC0 Memory Map
39
PCI Express* Interface Decode Rules
40
Legacy VGA and I/O Range Decode Rules
41
PEG Upstream VC0 Memory Map
41
IGD Frame Buffer Accesses
42
IGD VGA I/O Mapping
42
VGA and MDA I/O Transaction Mapping
43
Processor Register Introduction
45
I/O Mapped Registers
46
PCI Device 0 Function 0 Configuration Space
46
PCI Device 0, Function 0 Register Address Map
46
VID-Vendor Identification Register
48
DID-Device Identification Register
48
PCICMD-PCI Command Register
49
PCISTS-PCI Status Register
50
RID-Revision Identification Register
52
CC-Class Code Register
53
HDR-Header Type Register
53
SVID-Subsystem Vendor Identification Register
54
SID-Subsystem Identification Register
54
PXPEPBAR-PCI Express Egress Port Base Address Register
55
MCHBAR-Host Memory Mapped Register Range Base Register
56
GGC-GMCH Graphics Control Register Register
57
DEVEN-Device Enable Register
59
PCIEXBAR-PCI Express Register Range Base Address Register
60
DMIBAR-Root Complex Register Range Base Address Register
62
PAM0-Programmable Attribute Map 0 Register
63
PAM1-Programmable Attribute Map 1 Register
64
PAM2-Programmable Attribute Map 2 Register
65
PAM3-Programmable Attribute Map 3 Register
66
PAM4-Programmable Attribute Map 4 Register
67
PAM5-Programmable Attribute Map 5 Register
68
PAM6-Programmable Attribute Map 6 Register
69
LAC-Legacy Access Control Register
70
REMAPBASE-Remap Base Address Register
74
REMAPLIMIT-Remap Limit Address Register
74
TOM-Top of Memory Register
75
TOUUD-Top of Upper Usable DRAM Register
76
BDSM-Base Data of Stolen Memory Register
77
BGSM-Base of GTT Stolen Memory Register
77
G Memory Base Register
78
TOLUD-Top of Low Usable DRAM Register
78
SKPD-Scratchpad Data Register
79
CAPID0_A-Capabilities a Register
80
PCI Device 1 Function 0-2 Configuration Space
82
PCI Device 1, Function 0-2 Configuration Register Address Map
82
VID1-Vendor Identification Register
84
DID1-Device Identification Register
84
PCICMD1-PCI Command Register
85
PCISTS1-PCI Status Register
87
RID1-Revision Identification Register
89
CC1-Class Code Register
89
CL1-Cache Line Size Register
90
HDR1-Header Type Register
90
PBUSN1-Primary Bus Number Register
90
SBUSN1-Secondary Bus Number Register
91
SUBUSN1-Subordinate Bus Number Register
91
IOBASE1-I/O Base Address Register
92
IOLIMIT1-I/O Limit Address Register
92
SSTS1-Secondary Status Register
93
MBASE1-Memory Base Address Register
94
MLIMIT1-Memory Limit Address Register
95
PMBASE1-Prefetchable Memory Base Address Register
96
PMLIMIT1-Prefetchable Memory Limit Address Register
97
PMBASEU1-Prefetchable Memory Base Address Upper Register
98
PMLIMITU1-Prefetchable Memory Limit Address Upper Register
98
CAPPTR1-Capabilities Pointer Register
99
INTRLINE1-Interrupt Line Register
99
INTRPIN1-Interrupt Pin Register
100
BCTRL1-Bridge Control Register
100
PM_CAPID1-Power Management Capabilities Register
102
PM_CS1-Power Management Control/Status Register
103
SS_CAPID-Subsystem ID and Vendor ID Capabilities Register
104
SS-Subsystem ID and Subsystem Vendor ID Register
105
MSI_CAPID-Message Signaled Interrupts Capability ID Register
105
MC-Message Control Register
106
MA-Message Address Register
107
MD-Message Data Register
107
PEG_CAPL-PCI Express-G Capability List Register
107
DCAP-Device Capabilities Register
108
PEG_CAP-PCI Express-G Capabilities Register
108
DCTL-Device Control Register
109
DSTS-Device Status Register
110
LCTL-Link Control Register
111
LSTS-Link Status Register
113
SLOTCAP-Slot Capabilities Register
114
SLOTCTL-Slot Control Register
116
SLOTSTS-Slot Status Register
118
LCTL2-Link Control 2 Register
120
RCTL-Root Control Register
120
PCI Device 1 Function 0-2 Extended Configuration
123
PVCCAP1-Port VC Capability Register 1
123
PCI Device 1 Function 0-2 Extended Configuration Register Address Map
123
PVCCAP2-Port VC Capability Register 2
124
PVCCTL-Port VC Control Register
124
VC0RCAP-VC0 Resource Capability Register
125
VC0RCTL-VC0 Resource Control Register
126
VC0RSTS-VC0 Resource Status Register
127
PEG_TC-PCI Express Completion Time-Out Register
127
PCI Device 2 Configuration Space
128
PCI Device 2 Configuration Register Address Map
128
VID2-Vendor Identification Register
129
DID2-Device Identification Register
129
PCICMD2-PCI Command Register
130
PCISTS2-PCI Status Register
131
RID2-Revision Identification Register
132
CC-Class Code Register
132
CLS-Cache Line Size Register
133
MTXT2-Master Latency Timer Register
133
HDR2-Header Type Register
133
GTTMMADR-Graphics Translation Table, Memory Mapped Range Address Register
134
GMADR-Graphics Memory Range Address Register
135
IOBAR-I/O Base Address Register
136
SVID2-Subsystem Vendor Identification Register
136
SID2-Subsystem Identification Register
137
ROMADR-Video BIOS ROM Base Address Register
137
INTRPIN-Interrupt Pin Register
137
MINGNT-Minimum Grant Register
138
MAXLAT-Maximum Latency Register
138
MSAC-Multi Size Aperture Control Register
139
Device 2 IO
140
DATA-MMIO Data Register
140
INDEX-MMIO Address Register
140
PCI Device 6
141
PCI Device 6 Register Address Map
141
DID6-Device Identification Register
143
VID6-Vendor Identification Register
143
PCICMD6-PCI Command Register
144
PCISTS6-PCI Status Register
146
CC6-Class Code Register
148
RID6-Revision Identification Register
148
CL6-Cache Line Size Register
149
HDR6-Header Type Register
149
PBUSN6-Primary Bus Number Register
149
SBUSN6-Secondary Bus Number Register
150
SUBUSN6-Subordinate Bus Number Register
150
IOBASE6-I/O Base Address Register
151
IOLIMIT6-I/O Limit Address Register
151
SSTS6-Secondary Status Register
152
MBASE6-Memory Base Address Register
153
MLIMIT6-Memory Limit Address Register
154
PMBASE6-Prefetchable Memory Base Address Register
155
PMLIMIT6-Prefetchable Memory Limit Address Register
156
PMBASEU6-Prefetchable Memory Base Address Upper Register
157
PMLIMITU6-Prefetchable Memory Limit Address Upper Register
158
CAPPTR6-Capabilities Pointer Register
158
INTRLINE6-Interrupt Line Register
159
INTRPIN6-Interrupt Pin Register
159
BCTRL6-Bridge Control Register
160
PM_CAPID6-Power Management Capabilities Register
162
PM_CS6-Power Management Control/Status Register
163
SS_CAPID-Subsystem ID and Vendor ID Capabilities Register
164
SS-Subsystem ID and Subsystem Vendor ID Register
165
MSI_CAPID-Message Signaled Interrupts Capability ID Register
165
MC-Message Control Register
166
MA-Message Address Register
167
MD-Message Data Register
167
PEG_CAPL-PCI Express-G Capability List Register
167
PEG_CAP-PCI Express-G Capabilities Register
168
DCAP-Device Capabilities Register
168
DCTL-Device Control Register
169
DSTS-Device Status Register
170
LCTL-Link Control Register
171
LSTS-Link Status Register
173
SLOTCAP-Slot Capabilities Register
174
SLOTCTL-Slot Control Register
176
SLOTSTS-Slot Status Register
178
RCTL-Root Control Register
179
PCI Device 6 Extended Configuration
180
PVCCAP1-Port VC Capability Register 1
180
PCI Device 6 Extended Configuration Register Address Map
180
PVCCAP2-Port VC Capability Register 2
181
PVCCTL-Port VC Control Register
181
VC0RCAP-VC0 Resource Capability Register
182
VC0RCTL-VC0 Resource Control Register
183
VC0RSTS-VC0 Resource Status Register
184
Dmibar
185
DMIVCECH-DMI Virtual Channel Enhanced Capability Register
186
DMIPVCCAP1-DMI Port VC Capability Register 1
187
DMIPVCCAP2-DMI Port VC Capability Register 2
187
DMIPVCCTL-DMI Port VC Control Register
188
DMIVC0RCAP-DMI VC0 Resource Capability Register
188
DMIVC0RCTL-DMI VC0 Resource Control Register
189
DMIVC0RSTS-DMI VC0 Resource Status Register
190
DMIVC1RCAP-DMI VC1 Resource Capability Register
190
DMIVC1RCTL-DMI VC1 Resource Control Register
191
DMIVC1RSTS-DMI VC1 Resource Status Register
192
DMIVCPRCAP-DMI Vcp Resource Capability Register
192
DMIVCPRCTL-DMI Vcp Resource Control Register
193
DMIVCPRSTS-DMI Vcp Resource Status Register
194
DMIESD-DMI Element Self Description Register
195
DMILE1A-DMI Link Entry 1 Address Register
196
DMILE1D-DMI Link Entry 1 Description Register
196
DMILE2A-DMI Link Entry 2 Address Register
197
DMILE2D-DMI Link Entry 2 Description Register
197
LCAP-Link Capabilities Register
198
LCTL-Link Control Register
199
LSTS-DMI Link Status Register
200
LCTL2-Link Control 2 Register
201
LSTS2-Link Status 2 Register
203
MCHBAR Registers in Memory Controller - Channel 0
204
Pm_Pdwn_Config_C0-Power-Down Configuration Register
204
MCHBAR Registers in Memory Controller - Channel 0 Register Address Map
204
TC_RFP_C0-Refresh Parameters Register
205
TC_RFTP_C0-Refresh Parameters Register
205
MCHBAR Registers in Memory Controller - Channel 1
206
Pm_Pdwn_Config_C1-Power-Down Configuration Register
206
MCHBAR Registers in Memory Controller - Channel 1 Register Address Map
206
TC_RFP_C1-Refresh Parameters Register
207
TC_RFTP_C1-Refresh Timing Parameters Register
207
MCHBAR Registers in Memory Controller - Integrated Memory Peripheral Hub (IMPH)
208
CRDTCTL3-Credit Control 3 Register
208
MCHBAR Registers in Memory Controller - Integrated Memory Peripheral Hub
208
MCHBAR Registers in Memory Controller - Common
209
MAD_CHNL-Address Decoder Channel Configuration Register
209
MCHBAR Registers in Memory Controller - Common Register Address Map
209
Mad_Dimm_Ch0-Address Decode Channel 0 Register
210
Mad_Dimm_Ch1 - Address Decode Channel 1 Register
211
Pm_Sref_Config-Self Refresh Configuration Register
212
Memory Controller MMIO Registers Broadcast Group
213
Pm_Pdwn_Config-Power-Down Configuration Register
213
Memory Controller MMIO Registers Broadcast Group Register Address Map
213
PM_CMD_PWR-Power Management Command Power Register
214
Pm_Bw_Limit_Config-BW Limit Configuration Register
214
Integrated Graphics Vtd Remapping Engine Registers
215
Integrated Graphics Vtd Remapping Engine Register Address Map
215
VER_REG-Version Register
216
CAP_REG-Capability Register
217
ECAP_REG-Extended Capability Register
220
GCMD_REG-Global Command Register
222
GSTS_REG-Global Status Register
225
RTADDR_REG-Root-Entry Table Address Register
226
CCMD_REG-Context Command Register
227
FSTS_REG-Fault Status Register
229
FECTL_REG-Fault Event Control Register
231
FEDATA_REG-Fault Event Data Register
232
FEADDR_REG-Fault Event Address Register
232
FEUADDR_REG-Fault Event Upper Address Register
232
AFLOG_REG-Advanced Fault Log Register
233
PMEN_REG-Protected Memory Enable Register
234
PLMBASE_REG-Protected Low-Memory Base Register
235
PLMLIMIT_REG-Protected Low-Memory Limit Register
236
PHMBASE_REG-Protected High-Memory Base Register
237
PHMLIMIT_REG-Protected High-Memory Limit Register
238
IQH_REG-Invalidation Queue Head Register
239
IQT_REG-Invalidation Queue Tail Register
239
IQA_REG-Invalidation Queue Address Register
240
ICS_REG-Invalidation Completion Status Register
240
IECTL_REG-Invalidation Event Control Register
241
IEDATA_REG-Invalidation Event Data Register
242
IEUADDR_REG-Invalidation Event Upper Address Register
242
IRTA_REG-Interrupt Remapping Table Address Register
243
IVA_REG-Invalidate Address Register
244
IOTLB_REG-IOTLB Invalidate Register
245
FRCDL_REG-Fault Recording Low Register
247
FRCDH_REG-Fault Recording High Register
248
VTPOLICY-DMA Remap Engine Policy Control Register
249
PCU MCHBAR Registers
250
PCU MCHBAR Register Address Map
250
MEM_TRML_ESTIMATION_CONFIG-Memory Thermal Estimation Configuration Register
251
MEM_TRML_THRESHOLDS_CONFIG-Memory Thermal Thresholds Configuration Register
252
MEM_TRML_STATUS_REPORT-Memory Thermal Status Report Register
253
MEM_TRML_TEMPERATURE_REPORT-Memory Thermal Temperature Report Register
254
MEM_TRML_INTERRUPT-Memory Thermal Interrupt Register
254
GT_PERF_STATUS-GT Performance Status Register
255
RP_STATE_CAP-RP State Capability Register
255
SSKPD-Sticky Scratchpad Data Register
256
Pxpepbar
258
EPVC0RCTL-EP VC 0 Resource Control Register
258
Default PEG/DMI Vtd Remapping Engine Registers
259
Default PEG/DMI Vtd Remapping Engine Register Address Map
259
VER_REG-Version Register
260
CAP_REG-Capability Register
261
ECAP_REG-Extended Capability Register
264
GCMD_REG-Global Command Register
266
GSTS_REG-Global Status Register
269
RTADDR_REG-Root-Entry Table Address Register
270
CCMD_REG-Context Command Register
271
FSTS_REG-Fault Status Register
273
FECTL_REG-Fault Event Control Register
275
FEDATA_REG-Fault Event Data Register
276
FEADDR_REG-Fault Event Address Register
276
FEUADDR_REG-Fault Event Upper Address Register
276
AFLOG_REG-Advanced Fault Log Register
277
PMEN_REG-Protected Memory Enable Register
278
PLMBASE_REG-Protected Low-Memory Base Register
279
PLMLIMIT_REG-Protected Low-Memory Limit Register
280
PHMBASE_REG-Protected High-Memory Base Register
281
PHMLIMIT_REG-Protected High-Memory Limit Register
282
IQH_REG-Invalidation Queue Head Register
283
EG-Invalidation Queue Tail Register
283
IQA_REG-Invalidation Queue Address Register
284
ICS_REG-Invalidation Completion Status Register
284
IECTL_REG-Invalidation Event Control Register
285
IEDATA_REG-Invalidation Event Data Register
286
IEADDR_REG-Invalidation Event Address Register
286
IEUADDR_REG-Invalidation Event Upper Address Register
287
IRTA_REG-Interrupt Remapping Table Address Register
287
IVA_REG-Invalidate Address Register
288
IOTLB_REG-IOTLB Invalidate Register
289
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