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4.5
System Memory Layout Guidelines
4.5.1
System Memory Solution Space
Figure 4-5. System Memory Topologies
Topology 1
Topology 2
Topology 3
Topology 4
Topology 5
Table 4-1. System Memory Routing
Signal
Top.
SCS[3:2]#
Opt.1
Opt.2
Opt.3
SCS[1:0]#
Opt.1
Opt.2
Opt.3
SMAA[7:4]
SMAB[7:4]#
SCKE[1:0]
SMD[63:0],
SDQM[7:0]
SCAS#,
SRAS#,
SWE#
SBS[1:0],
SMAA[11:8,
3:0]
NOTE: It is recommended to add 10 Ω series resistors to the MAA[7:4] and the MAB[7:4] lines as close as
possible to GMCH for signal integrity.
®
Intel
810A3 Chipset Design Guide
G M C H
A
A
Trace (mils)
A
Width
Space
Max
5
10
8
5
10
8
5
10
8
4
10
8
4
10
8
4
10
8
1
10
8
0.5
2
10
8
0.5
3
10
8
3
5
7
3
5
7
3
5
7
10 ohm
B
10 ohm
C
A
D
A
D
A
E
Trace Lengths (inches)
B
C
Min
Max
Min
Max
Min
3
2.2
1.6
0.5
2
0.5
2
1
1
1
1
Layout and Routing Guidelines
D I M M 0
D I M M 1
F
G
D
E
F
Max
Min
Max
Min
Max
3
5
2.2
5
1.6
5
5
5
5
2.5
0.4
1
3
0.4
1
3.5
0.4
1
2.5
0.4
1
G
G
Min
Max
1.5
2
1.5
1.8
1.15
1.5
1.5
2
1.5
1.8
1.15
1.5
4-5
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